Lecture Slides on Register Transfers and Datapath | COMP SCI 352, Study notes of Computer Science

Download Lecture Slides on Register Transfers and Datapath | COMP SCI 352 and more Study notes Computer Science in PDF only on Docsity! 1 University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 7 Register Transfers & Datapaths Originals by: Charles R. Kime Modified for course use by: Kewal K. Saluja and Yu Hen Hu © 2001 Prentice Hall, Inc Logic and Computer Design Fundamentals Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 2 Overview of Chapter 7 § Review from Chapter 1 § Datapath and Control Unit § Register Transfer Operations § Microoperations § Register Transfer Structures • Multiplexer based • Bus based • Three state bus • Memory transfer • Other transfer § Datapath § ALU § Shifter and Barrel Shifter § Datapath Representation and Control § Pipelined Datapath Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 3 Review from Chapter 1: Computer Diagram § CPU (Central Processing Unit): Performs sequences of processing operations on data stored in memory and interacts with Input/Output § Datapath: Performs basic operation on data stored in registers as directed by Control. § Control: Determines the sequence of data processing operations to be performed in the Datapath. § Memory: An addressable repository for data § Input/Output: A collection of devices that store, display and convert information. Memory Control DatapathCPU Input/Output Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 4 Datapath and Control Unit § Control: signals that configure data transfers and establish operations to be performed. § Status: signals that represent the state of data, such as overflow bits, "zero" tests, etc. These signals are tested to change the sequence of operations Control Inputs Control Unit Control Status Datapath Control Outputs Data Inputs Data Outputs Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 5 Register Transfer Operations § Registers – a collection of binary storage flip- flops organized in a logical fashion. § Register Transfer Operations – The movement and processing of data stored in registers § Three basic components: • set of registers • operations • control of operations § Elementary Operations -- load, count, shift, add, bitwise "OR", etc. • Elementary operations are called microoperations Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 6 Register Transfer § Register Notation • Letters and numbers – denotes a register (ex. R2, PC, IR) • Parentheses ( ) – denotes a range of register bits (ex. R1(1), PC(7:0), AR(L)) • Arrow (← ) – denotes data transfer (ex. R1 ← R2, PC(L) ← R0) • Comma – separates parallel operations • Brackets [ ] – Specifies a memory address (ex. R0 ← M[AR], R3 M[PC] ) R 7 6 5 4 3 2 1 0 15 8 7 0 15 0 PC(H) PC(L) R2 2 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 7 Conditional Transfer § If (K1 =1) then (R2 ← R1) is shortened to K1: (R2 ← R1) where K1 is a control variable specifying a conditional execution. condition. § Conditional execution is used to modify the sequence of microoperations. R1 R2 K1 Clock Load n Clock K1 Transfer Occurs Here Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 8 Microoperations § Logical Groupings: • Transfer -- move data from one set of registers to another. • Arithmetic -- perform arithmetic on data in registers. • Logic -- manipulate data or use bitwise logical operations. • Shift -- shift data in registers. Arithmetic operations (word-wide) + Addition – Subtraction * Multiplication / Division Logical operations (bitwise) ∨ Logical OR ∧ Logical AND ⊕ Logical Exclusive OR  Not Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 9 Example Microoperations § Add the content of R1 to the content of R2 and place the result in R1. R1← R1 + R2 § Multiply the content of R1 by the content of R6 and place the result in PC. PC ← R1 * R6 § Exclusive OR the content of R1 with the content of R2 and place the result in R1. R1 ← R1 ⊕ R2 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 10 Example Microoperations (Continued) § Take the 1's Complement of the contents of R2 and place it in the PC. § PC ← R2 § On condition K1 OR K2, Logical bitwise OR the content of R1 with the content of R3 and place the result in R1. § (K1 + K2): R1 ← R1 ∨ R3 § NOTE: "+" (as in K1 + K2) and means “OR.” In R1 ← R1 + R3, + means “plus.” Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 11 Control Expressions § The control expression for an operation appears to the left of the operation and is separated from it by a colon § Control expressions specify the logical conditions for the operation to occur § Control expression values of: § Logic "1" -- the operation takes place. § Logic "0" -- the operation is inhibited. § Examples: X K1 : R1 ← R1 + R2 X K1 : R1 R1 + R2' + 1 § Variable K1 enables the add or subtract operation. § If X =0, then X =1 so X K1 = 1, activating the add of R1 and R2. § If X =1, then X K1 = 1, activating the add of R1 and the two's comp. of R2 (subtract). Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 12 Arithmetic Microoperations § From Table 7-3: § Note that any register may be specified for source 1, source 2, or destination. § These simple microoperations operate on the whole word -- except for 1's complement which is a bitwise operation. Symbolic Designation Description R0 ← R1 + R2 Addition R0 ← R1 Ones Complement R0 ← R1 + 1 Two's Complement R0 ← R2 + R1 + 1 R2 minus R1 (2's Comp) R1 ← R1 + 1 Increment (count up) R1 ← R1 – 1 Decrement (count down) 5 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 25 Other Transfer Structures § Fast systems require that parallel operations occur within the same clock. § Parallel operations imply "resources" required to move the data. § SO: • Multiple buses are used, and • Multiplexers are used to select input sources. § THIS REQUIRES MORE HARDWARE! Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 26 Other Transfer Structures (Continued) § What transfers does this system allow? S2 L0 n R0 Load n E0a n E0b n n MUX S0 1 L1 n R1 Load n E1a n E1b n n MUX S0 1 L2 n R2 Load n E2a n E2b n n MUX S0 1 S1 S0 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 27 Datapath § Unit that can perform multiple functions and store results – often contains functional units (such as ALU, shifter) and register file § Example Figure 7-9 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 28 2 00 || Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 29 ALU, Shifter and Barrel Shifter § ALU • Can perform multiple operations such as add, subtract, and, or, EOR, increment, decrement, transfer – see table 7 - 8 for an example set of operations • Realization § Mux based: figure 7-15 § Further reduction of logic possible using logic minimization methods § Shifter, Barrel Shifter • Can be used for one or multiple bit shifts • Mux based realizations given in Figures 7 -16 and 7 -17 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 30 N-bit ALU (Fig 7-10) 6 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 31 An Arithmetic Circuit Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 32 B input logic for one stage of Arithmetic Unit Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 33 4-bit Arithmetic Unit Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 34 1-stage of logic unit Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 35 1 stage of ALU Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 36 4-bit basic shifter 7 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 37 4-bit Barrel Shifter Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 38 Datapath Representation and Control § Datapath representation • See Figure 7 -18 • Control signals (for function unit) are shown – see Table 7-10 § Control • Control variables and functions of datapath shown in Figure 7 -19 and Table 7 -11 Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 39 Data Path Logic and Computer Design Fundamentals © 2001 Prentice Hall, Inc Chapter 7 40 Pipelined Datapath § A method of improving performance § Tradeoff between latency and throughput • Increases clock frequency • Many clock cycles to complete the job