VLSI Design: Understanding Resistance and Static CMOS Inverters - Prof. Aurangzeb Khan, Study notes of Electrical and Electronics Engineering

Download VLSI Design: Understanding Resistance and Static CMOS Inverters - Prof. Aurangzeb Khan and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! EE534 VLSI Design System Resistance and Static CMOS inverter CMOS Inverter: Dynamic VDD Rn Vout = 0 Vin = V DD CL tpHL = f(Rn, CL) Last lecture’s focus Today’s focus Transient, or dynamic, response determines the maximum speed at which a device can be operated. Review: Sources of Capacitance Vout Cw Vin CDB2 CDB1 CGD12 M2 M1 M4 M3 Vout2 CG4 CG3 wiring (interconnect) capacitance intrinsic MOS transistor capacitances Vout2Vin extrinsic MOS transistor (fanout) capacitances Vout CL Sources of Resistance MOS structure resistance - Ron Source and drain resistance Contact (via) resistance Wiring resistance Top view Drain n+ Source n+ W L Poly Gate MOS Structure Resistance The simplest model assumes the transistor is a switch with an infinite “off” resistance and a finite “on” resistance Ron However Ron is nonlinear, so use instead the average value of the resistances, Req, at the end-points of the transition (VDD and VDD/2) Req = ½ (Ron(t1) + Ron(t2)) Req = ¾ VDD/IDSAT (1 – 5/6 λ VDD) S D Ron VGS ≥ VT Equivalent MOS Structure Resistance For VDD>>VT+VDSAT/2, Req is independent of VDD (see plot). Only a minor improvement in Req occurs when VDD is increased (due to channel length modulation) Once the supply voltage approaches VT, Req increases dramatically 313855115PMOS (kΩ) 13151935NMOS(kΩ) 2.521.51VDD(V) Req (for W/L = 1), for larger devices divide Req by W/L VDD (V) R eq (O hm ) x105 (for VGS = VDD, VDS = VDD→VDD/2) 0 1 2 3 4 5 6 7 0.5 1 1.5 2 2.5 The on resistance is inversely proportional to W/L. Doubling W halves Req Source and Drain Resistance More pronounced with scaling since junctions are shallower With silicidation R is reduced to the range 1 to 4 Ω/ RS RD S G D RS,D = (LS,D/W)R where LS,D is the length of the source or drain diffusion R is the sheet resistance of the source or drain diffusion (20 to 100 Ω/ ) Contact Resistance Transitions between routing layers (contacts through via’s) add extra resistance to a wire keep signals wires on a single layer whenever possible avoid excess contacts reduce contact resistance by making vias larger (beware of current crowding that puts a practical limit on the size of vias) or by using multiple minimum-size vias to make the contact Typical contact resistances, RC, (minimum-size) 5 to 20 Ω for metal or poly to n+, p+ diffusion and metal to poly 1 to 5 Ω for metal to metal contacts More pronounced with scaling since contact openings are smaller Wire Spacing Comparisons Intel P856.5 Al, 0.25µm Ω - 0.33 M2 Ω - 0.33 M3 Ω - 0.12 M4 Ω - 1.11 M1 Ω - 0.05 M5 Scale: 2,160 nm Ω - 0.49 M2 Ω - 0.49 M3 Ω - 0.17 M4 Ω - 1.00 M1 Ω - 0.08 M5 Ω - 0.07 M6 Intel P858 Al, 0.18µm IBM CMOS-8S CU, 0.18µm Ω - 0.97 M1 Ω - 0.10 M6 Ω - 0.10 M7 Ω - 0.70 M2 Ω - 0.50 M3 Ω - 0.50 M4 Ω - 0.50 M5 From MPR, 2000 Design Abstraction Levels SYSTEM GATE CIRCUIT VoutVin MODULE + DEVICE n+ S D n+ G At present, complementary MOS or CMOS has replaced NMOS at all level of integration, in both analog and digital applications. The basic reason of this replacement is that the power dissipation in CMOS logic circuits is much less than in NMOS circuits, which makes CMOS very attractive. Although the processing is more complicated for CMOS circuits than for NMOS circuits. However, the advantages of CMOS digital circuits over NMOS circuits justify their use. CMOS: the most abundant devices on earth Simplified cross section of a CMOS inverter In the fabrication process, a separate p-well region is formed within the starting n-substrate. The n-channel MOSFET is fabricated in the p-well region and p-channel MOSFET is fabricated in the n- substrate. CMOS Inverter: A First Look VDD Vout CL Vin CMOS Properties Full rail-to-rail swing ⇒ high noise margins Logic levels not dependent upon the relative device sizes ⇒ transistors can be minimum size ⇒ ratioless Always a path to Vdd or GND in steady state ⇒ low output impedance (output resistance in kΩ range) ⇒ large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) ⇒ nearly zero steady-state input current No direct path steady-state between power and ground ⇒ no static power dissipation Propagation delay function of load capacitance and resistance of transistors Voltage Transfer Characteristic DC analysis of the CMOS inverter The figure shows series combination of a CMOS inverter. To form the input, gate of the two MOSFET are connected. To form the output, the drains are connected together. VI Vo 1 0 0 1 The transistor KN is also known as “pull down” Device, it is pulling the output voltage down towards ground. The transistor KP is known as the “pull up” device because it is pulling the output voltage up towards VDD. This property speed up the operation considerably. It is to be noted that the static power dissipation during both extreme cases (logic 1 or 0) is almost zero because iDp=iDn=0. 7 VGS,n = Vin VDS,n = Vout Vou t= VOH = VDD Vout = VOL = 0 Review: Short Channel I-V Plot (NMOS) 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 I D (A ) VDS (V) X 10-4 VGS = 1.0V VGS = 1.5V VGS = 2.0V VGS = 2.5V Li ne ar d e p e nd e n c e NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V Review: Short Channel I-V Plot (PMOS) -1 -0.8 -0.6 -0.4 -0.2 0 0-1-2 I D (A ) VDS (V) X 10-4 VGS = -1.0V VGS = -1.5V VGS = -2.0V VGS = -2.5V PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V All polarities of all voltages and currents are reversed CMOS Static Inverter design consideration CMOS inverter design consideration The CMOS inverter usually design to have, (i) VTN =|VTP| (ii) K´n(W/L)=K´p(W/L) But K´n> K´p (because µn>µp) How equation (ii) can be satisfied? This can be achieved if width of the PMOS is made two or three times than that of the NMOS device. This is very important in order to provide a symmetrical VTC, results in wide noise margin. VCC VCC Vin Vout kp=kn kp=5kn kp=0.2kn • Increase W of PMOS kp increases VTC moves to right • Increase W of NMOS kn increases VTC moves to left • For VTH = Vcc/2 kn = kp Wn ≈ 2Wp CMOS inverter design consideration (cont.) 5.2≈=             p n n p L W L W µ µ CMOS inverter design consideration (cont.) CMOS inverter design consideration (cont.) Impact of Process Variation on VTC Curve 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 Vin (V) V ou t (V ) Nominal Good PMOS Bad NMOS Bad PMOS Good NMOS Process variations (mostly) cause a shift in the switching threshold Effects of Vth adjustment Result from changing kp/kn ratio: Inverter threshold VTH ≠ Vcc/2 Rise and fall delays unequal Noise margins not equal Reasons for changing inverter threshold Want a faster delay for one type of transition (rise/fall) Remove noise from input signal: increase one noise margin at expense of the other Symmetrical properties of the CMOS inverter Example: Mapping between analog and digital signals "1" "0" VOH VIH VIL VOL Undefined Region V(x) V(y) VOH VOL VIH V IL Slope = -1 Slope = -1 Definition of Noise Margins VIH VIL Undefined Region "1" "0" VOH VOL NMH NML Gate Output Gate Input Noise Margin High Noise Margin Low