Download CMOS Inverter Design: Static Operation and VTC Characteristics - Prof. Aurangzeb Khan and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! EE534 VLSI Design System Summer 2004 Lecture 06: Static CMOS inverter (CHAPTER 5) Review: CMOS Inverter VTC 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 Vin (V) V ou t (V ) NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off VDD Vout CL NMOS off PMOS in non sat NMOS in sat PMOS in non sat NMOS in sat PMOS in sat NMOS in non sat PMOS in sat NMOS in nonsat PMOS off Vout = VDS D ra in c ur re nt I D S Vin=2V VCC Vin=1V Vin=3V Vin=4V Review: CMOS Inverter: VTC Vout = VDS D ra in c ur re nt I D S Vin=2V VCC Vin=1V Vin=3V Vin=4V V ou t Vin1 2 3 40 VCC PMOS NMOS • Output goes completely to Vcc and Gnd • Sharp transition region CMOS Inverter: Switch Model of Dynamic Behavior VDD Rn Vout CL Vin = V DD VDD Rp Vout CL Vin = 0 CMOS Inverter: Switch Model of Dynamic Behavior VDD Rn Vout CL Vin = V DD VDD Rp Vout CL Vin = 0 Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn) CMOS inverter operation NMOS transistor: Cutoff if Vin < VTN Linear if Vout < Vin – VTN Saturated if Vout > Vin – VTN PMOS transistor Cutoff if (Vin-VCC) < VTP → Vin < Vcc+VTP Linear if (Vout-VCC)>Vin-Vcc-VTP → Vout>Vin - VTP Sat. if (Vout-VCC)<Vin-Vcc-VTP → Vout < Vin-VTP Vin Vout Vcc CMOS Static Inverter design consideration Definition of Noise Margins VIH VIL Undefined Region "1" "0" VOH VOL NMH NML Gate Output Gate Input Noise Margin High Noise Margin Low Concept of Noise Margins NML=VIL-VOL (noise margin for low input) NMH=VOH-VIH (noise margin for high input) VI ILOLILL VVVNM =−= ILIHCCIHOHH VVVVVNM =−=−= Noise margin calculations Vout = VDS D ra in c ur re nt I D S Vin=2V VCC Vin=1V Vin=3V Vin=4V CMOS inverter: VIL KCL: IDp=IDn Differentiate and set dVout/dVin to –1 Solve simultaneously with KCL to find VIL ( ) ( )[ ]2,,,0,2,0, 222 pDSpDSpTpGS p nTnGS n VVVV k VVk −−=− ( ) ( )( ) ( )[ ]2,02,0 222 CCoutCCoutpTCCin p nTin n VVVVVVV k VVk −−−−−=− ( ) ( ) ( ) ( ) −−−+−−=− in out CCoutCCout in out pTCCinpnTinn dV dVVVVV dV dVVVVkVVk ,0,0 ( ) ( )CCpTILoutpnTILn VVVVkVVk −+−=− ,0,0 2 R nTRCCpTout IL k VkVVV V + +−+ = 1 2 ,0,0 p n R k kk = CMOS inverter: VIH KCL: Differentiate and set dVout/dVin to –1 Solve simultaneously with KCL to find VIH ( )[ ] ( )2,0,2,,,0, 222 pTpGS p nDSnDSnTnGS n VV k VVVVk −=−− ( )[ ] ( )2,02,0 222 pTCCin p outoutnTin n VVV k VVVVk −−=−− ( ) ( )pTCCinp in out outout in out nTinn VVVkdV dVVV dV dVVVk ,0,0 −−= −+− ( ) ( )pTCCIHppTIHoutn VVVkVVVk ,0,02 −−=+− ( ) R nToutRpTCC IH k VVkVV V + +++ = 1 2 ,0,0 p n R k kk = CMOS inverter: VIL and VIH for Ideal VTH (Symmetrical, Kn=Kp) Assuming VT0,n=-VT0,p, and kR = 1, ( )0238 1 TCCIL VVV += ( )0258 1 TCCIH VVV −= DDIHIL VVV =+ ILOLILL VVVNM =−= ILIHCCIHOHH VVVVVNM =−=−= (symmetrical inverter) Example 5.4 CMOS inverter: VTH KCL: Solve for VTH = Vin = Vout ( ) ( )2,0,2,0, 22 pTpGS p nTnGS n VV k VVk −=− ( ) ( )2,02,0 22 pTCCin p nTin n VVV k VVk −−=− ( ) R pTCC R nT TH k VV k V V 11 1 ,0,0 + ++ = p n R k kk = CMOS inverter: Ideal VTH (Symmetrical, Kn=Kp) Ideally, Vth = VCC/2 Assuming VT0,n = VT0,p, ( ) R pTCC R nT TH k VV k V V 11 1 ,0,0 + ++ = p n R k kk = 2 ,0 ,0 , 2 2 + + = nTCC pTCC idealR VV VV k 1, =idealRk 5.2≈= p n n p L W L W µ µ nn L W L W ≈ 5.2⇒ For ideal symmetrical inverter required that
