ASIC Project Cost: Understanding Fixed and Variable Costs - Prof. Victor Nelson, Study notes of Electrical and Electronics Engineering

Download ASIC Project Cost: Understanding Fixed and Variable Costs - Prof. Victor Nelson and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! ASIC Project Cost Smith Text – Chapter 1 VLSI Implementations Custom Standard cell Gate array FPGA Density Highest Medium Low Lowest Performance Highest Medium Low Lowest Design time Long Medium Short Shortest Chip Dev cost High Medium Low Lowest Testability Difficult Less difficult Easy Easy High Volume? High Medium Low Lowest ASIC Cost: Variable (RE) Variable costs (cost per part) Wafer cost Wafer processing Die size (# die per wafer) Size of design (# gates) Technology (# gates per sq. inch) % utilization of die Production yield = f(defect density,die size) Packaging ASIC Fixed Costs Example MGA $2,000 Days Cost/iday Hardware $10,000 $20,000 $20,000 Size (gates) Gates/day Days Cost/day Design for test: $2,000 Days 5 Cost/day $400 NRE: $30,000 Masks $10,000 Simulation $10,000 Test program $10,000 Second source: Days Cost/day Total fixed costs $21,800 $86,000 CBIC $2,000 $10,000 $40,000 $20,000 $2,000 5 $400 $70,000 $50,000 $10,000 $10,000 $146,000 ASIC Variable Costs Example Density Utilization Die size Diefwafer Defect density Yield Die cost Profit margin Price/gate Part cost Units inches $ gates gates/sq.cm % sq.cm defects/sq.cm