Computer Architecture Midterm 1 - CS152, University of California, Berkeley, Exams of Computer Architecture and Organization

Download Computer Architecture Midterm 1 - CS152, University of California, Berkeley and more Exams Computer Architecture and Organization in PDF only on Docsity! University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Science Spring 2000 Prof. Bob Brodersen Midterm 1 March 15, 2000 CS152: Computer Architecture This midterm consists of four problems, each of which has multiple parts, so budget your time accordingly. The exam is closed-book, but calculators and one sheet of notes are allowed. Good luck! Name SOLUTIONS SID Discussion 1 2 3 4 Total Name __________________________________________________ Page 1 of 8 Problem 1: Critical Path and Delay (25 points) Throughout this problem, use the simple linear delay model presented in class. For the circuit below, assume the following delay parameters: NAND: tplh = 0.5ns, tphl = 0.5ns, tplhf = 0.002ns/fF, tphlf = 0.002ns/fF Input capacitance: 100fF Inverter: tplh = 0.2ns, tphl = 0.2ns, tplhf = 0.001ns/fF, tphlf = 0.001ns/fF Input capacitance: 50fF Wiring Capacitance: (Equal for all nodes) 5fF Y F Z X a) What is the worst case delay? Assume there is no delay at the inputs X, Y and Z. The equation for the worst case delay is as follows: .2ns+105fF*.001ns/fF (INVERTER) .5ns+205fF*.002ns/fF (NAND1) .5ns+205fF*.002ns/fF (NAND2) .5ns+105fF*.002ns/fF (NAND3 + .5ns+5fF*.002ns/fF (NAND4) = 3.345 ns Note: There is no delay at the input nodes, and remember to include fan-out and wiring delay! b) Now assume that you want to generate a symbol for the circuit in part (a). Determine the following parameters for your symbol: tplh, tphl, and the load dependant delay (in ns/fF). X Y F Z First the propagation delays: tplh = tphl, = 3.345 ns. This is the same as the critical path from the last part. For the load dependent delay, since we only have a single NAND driving the output, it is the same as the NAND itself: 0.002 ns/fF. Name __________________________________________________ Page 4 of 8 Diagram and scratch space for Problem 2: Name __________________________________________________ Page 5 of 8 6 Shifter 32 32 32 32 Lower ShAmt Upper Problem 3: Single-cycle Datapath Design (25 points) The task is to design a single cycle processor with the minimum number of functional units that can perform the following standard MIPS instructions plus a new rotate instruction. The rotate instruction does a rotate of $RS to the right by the IMMED value and stores it in $RD (e.g. a 2 shift rotate of a 5 byte word would turn [a b c d e] into [d e a b c]). The blocks that you can use are given below along with their control signals and delay values. All blocks are similar to those we used in class, except for the addition of a 64 bit shifter. Instructions: • ADDIU $RD $RS IMMED • ADD $RD $RS $RT • SRL $RD $RS IMMED • Rotate $RD $RS IMMED Components (and control signals): • ALU (ALUcontrol, Zero) => 32 bit ALU with Zero status bit – ALUcontrol = 00 for ADD, 01 for AND, 10 for SUB, 11 for OR Delay = 4 • EXTENDER (Sign/Zero) => Sign extender Delay = 1 • MUX (Select) => 2 input mux Delay = 1 • MEMORY (WrEnable, Addr) => Ideal memory Delay = 1 • REGISTER (Enable) => Clocked register Clk-to-Q Delay = 1 • REGISTER FILE (RD, RS, RT, WrEnable) => Register file Read delay = 1, Setup time = 1, Hold time = 1 • CONSTANTS => A 32 bit constant can be defined as an input to any block (no delay) • SHIFTER (ShAmt) => 64 bit shifter (see symbol below) – Input and output is through 2 buses which connect to the upper and lower 32 bits of a 64 bit word. Delay = 1 Name __________________________________________________ Page 6 of 8 a) Draw the datapath showing all interconnections and components (including the controller). b) What is the critical path ? The critical path is stressed on the ADD and ADDIU instructions. It includes the PC, instruction memory, register file, the ALUSrc mux, the ALU, the WrSrc mux, and the setup time for writing to the register file. c) What is the delay of the critical path? The sum of all the delays above is 10. Don’t forget the clock-to-Q of the PC and the setup time of the register file! d) Show the values of all the control points for each instruction. (The Enable for the PC is given as an example) PCEnable ALUSrc ALUOp Sign/Zero Rotate WrSrc ADDIU 1 0 00 Sign X 0 ADD 1 1 00 X X 0 SRL 1 X XX X 0 1 Rotate 1 X XX X 1 1