EECS 141: Fall 98 Final Exam - Electrical Engineering and Computer Science, Exams of Analog Electronics

Download EECS 141: Fall 98 Final Exam - Electrical Engineering and Computer Science and more Exams Analog Electronics in PDF only on Docsity! EECS 141: FALL 98 — FINAL 1 University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh9:30-11am ee141@eecs EECS 141: FALL 98 — FINAL For all problems, you can assume the following transistor parameters: NMOS: VTn = 0.75V, k’n = 20 µA/V2, λ = 0, γ = 0.5 V1/2, 2Φ F = -0.6V PMOS: VTp = -0.75V, k’p = 7 µA/V2, λ = 0, γ = 0.5 V1/2, 2Φ F = -0.6V NAME Last First GRAD/UNDERGRAD Total Problem 2: Problem 1: Problem 3: Problem 4: Problem 5: Problem 6: EECS 141: FALL 98 — FINAL 2 Problem 1: Logic Assume that the following network is part of a pass-transistor network. You may assume that the switches can be modeled by the following parameters: Ron = Req/W, Roff = infinity, and Cdb = Csb = Ceq * W (with W the width of the transistor). All other device capacitances can be ignored. The buffer has a delay equal to tbuf and an input capacitance equal to Cbuf. a. Determine the absolute minimum delay that can be obtained between input and output through sizing of the pass-transistors. Determine under what conditions that min- imum is obtained. M1 In Out Vdd Vdd Cbuf M2 (width W1) (width W2) EECS 141: FALL 98 — FINAL 5 d. Assuming that the following values hold: RL = RS = Z0/2, draw the voltage wave- forms at nodes X and Y for the first three times-of-flight. Indicate the signal values on the chart. e. Answer the following questions: - Will etching the dielectric material away and replacing it with air help to improve the performance of the interconnect network, and why? (assume that the circuit parame- ters are appropriately adjusted to the changing conditions) Yes / No - Assume that the original wire is implemented in Copper. Determine qualitatively if replacing the wiring material with Aluminum would hurt the performance and when this would happen? - Assume that the driver at the source of the interconnect line is a CMOS inverter. Similarly, the receiver at the end of the line is a CMOS inverter as well. Determine the preferred solution to minimize the propagation delay and power dissipation (pick one): Series termination at the source Series termination at the destination Parallel termination at the source Parallel termination at the destination EECS 141: FALL 98 — FINAL 6 PROBLEM 3: Interconnect Suppose you want to design a 3-stage buffer to drive a 75 pF capacitance. Vdd=3V. The first buffer gate is minimum size (in the 1.2 micron technology) and has an input gate capacitance of 20 fF. a. Determine the sizing of the buffers (6 transistors) to optimize delay. b. Determine that optimimum propagation delay. You may assume that the propagation delay of the minimum size gate delay loaded by an identical gate equals 175 psec. tp= EECS 141: FALL 98 — FINAL 7 c. Assuming that during the switching the current of an inverter rises linearly to a maxi- mum and then drops back linearly to zero (in a time interval approximately equal to 3.2 times tp), determine the maximum value of the voltage bounce on the supply rail, assum- ing that supply rails are connected to the supply with an inductance of 7.5 nH. . d. One way to reduce the voltage bounce is resizing the buffer. You are allowed to dou- ble the propagation delay of the driver to minimize the bounce. Describe your strategy, estimate the new sizes of the buffers, and determine the size of the bounce. ∆V= EECS 141: FALL 98 — FINAL 10 Problem 5: Sequential Circuits An astable multivibrator circuit is shown below. The Schmitt trigger is inverting and has a rail-to-rail swing. You may ignore the propagation delay of the Schmitt trigger (or assume that RC >> tp,schmitt). a. Draw the waveforms at the nodes Vi and Vo. b. Derive an expression for oscillation period as a function of the supply voltage, the Schmitt-trigger thresholds VM– and VM+, and the circuit parameters R and C. c. Describe what would happen if the Schmitt trigger would be replaced by a simple inverter. C R VoVi Multivibrator circuit. EECS 141: FALL 98 — FINAL 11 Problem 6. Timing Consider the two-ported register file cell shown below. a. The flip-flop highlighted in the Figure consists of a “strong” inverter (large sym- bol”) and a “weak” one. Explain what this means and why this design decision was made. b. Determine qualitatively the setup time of the flip-flop highlighted in the Figure as a function of the important design parameters (i.e. gate delays, rc-delays, etc). c. Determine qualitatively the propagation delay of the flip-flop as a function of the dominant design parameters. d. The clock experiences a nominal skew δ1 from the clock generator to point a (at the input of the flip-flop), and a nominal skew of δ2 from the clock generator to node b (see Figure). φ T X Y RBLWBL φ W Rδ1 δ2a b EECS 141: FALL 98 — FINAL 12 - Describe qualitatively under what circumstances the clock skew will cause a prob- lem. - Determine the maximum values of δ1 and δ2 so that the circuit will still be opera- tional. You may assume the following design parameters: tand and tinv are respectively the nominal propagation delays of the AND and inverter gates on the clock lines, while tpFF and tsFF are the nominal propagation delay and the set-up time of the flip-flop. It is also known that the clock skew can vary over 15% with respect to its nominal value (due to process variations), while the delays of the gates and the flip-flops can vary with 10%. e. Ascertain the minimum clock period, Tmin, as a function of the skew and the gate parameters. δ1max= δ2max= Tmin=