Measuring Power and Energy in VLSI Systems Design: Lecture 4 - Prof. Wr Davis, Study notes of Electrical and Electronics Engineering

Download Measuring Power and Energy in VLSI Systems Design: Lecture 4 - Prof. Wr Davis and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! Slide 1W. Rhett Davis NC State University ECE 546 Fall 2008 ECE 546 - VLSI Systems Design Lecture 4: Measuring Power, Parasitic Capacitances & Layout Fall 2008 W. Rhett Davis NC State University with significant material from Rabaey, Chandrakasan, and Nikolić Slide 2W. Rhett Davis NC State University ECE 546 Fall 2008 Announcements HW#1 Due Today HW#2 Due in 1 Week Layout Tutorial #1 Posted Slide 3W. Rhett Davis NC State University ECE 546 Fall 2008 Summary of Last Lecture What are the different components of the power of a gate? What are the different quality metrics for a gate and which one is best? Slide 4W. Rhett Davis NC State University ECE 546 Fall 2008 Today’s Lecture Measuring Power/Energy in SPICE (5.5.4) Parasitic Capacitances (3.2.3, 3.3) Processing Technology & Layout (2.2-2.3) Slide 9W. Rhett Davis NC State University ECE 546 Fall 2008 Measuring Short-Circuit Energy How to measure in HSPICE? 2 SCpeak DDSC tI VE = Slide 10W. Rhett Davis NC State University ECE 546 Fall 2008 Measuring Short-Circuit Energy Setup Vp and Vn as 0-volt sources Integrate the current through one of the sources to find QscHL & QscLH » Which one for HL? » Which one for LH? EscHL = VDDQscHL EscLH = VDDQscLH Slide 11W. Rhett Davis NC State University ECE 546 Fall 2008 What Wrong with this Picture? Why not connect Vn, Vp to source nodes? Slide 12W. Rhett Davis NC State University ECE 546 Fall 2008 Vout Overshoots Supply Rails Current injected back in supply from CGD1,2 Connecting Vp, Vn to source nodes would include this current Consider this part of Edyn V in / V ou t E to t Slide 13W. Rhett Davis NC State University ECE 546 Fall 2008 Energy Summary Etot = Total energy Delivered by Supply EscHL – measured through Vp (source btw. PMOS drain and Vout) EscLH – measured through Vn (source btw. NMOS drain and Vout) Edyn = Etot – EscHL – EscLH Slide 14W. Rhett Davis NC State University ECE 546 Fall 2008 Today’s Lecture Measuring Power/Energy in SPICE (5.5.4) Parasitic Capacitances (3.2.3, 3.3) Processing Technology & Layout (2.2-2.3) Slide 19W. Rhett Davis NC State University ECE 546 Fall 2008 Gate Capacitance WLCox WLCox 2 2WLCox 3 CGC CGCS VDS /(VGS-VT) CGCD 0 1 CGC CGCS = CGCDCGC B WLCox WLCox 2 VGS Capacitance as a function of VGS (with VDS = 0) Capacitance as a function of the degree of saturation Slide 20W. Rhett Davis NC State University ECE 546 Fall 2008 Gate Capacitance S D G CGC S D G CGC S D G CGC Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off (2/3)CoxWL0(2/3)CoxWL0Saturation CoxWLCoxWL/2CoxWL/20Resistive CoxWL00CoxWLCutoff CGCCGCDCGCSCGCBOperation Region Slide 21W. Rhett Davis NC State University ECE 546 Fall 2008 Computing CGB, CGS, & CGD Need to add the overlap capacitances to the channel capacitance COW(2/3)CoxWL + COW0Saturation (1/2)CoxWL + COW(1/2)CoxWL + COW0Resistive COWCOWCoxWLCutoff CGDCGSCGBOperation Region Slide 22W. Rhett Davis NC State University ECE 546 Fall 2008 Diffusion Capacitance: CSB & CDB Bottom Side wall Side wall Channel Source ND Channel-stop implant NA1 Substrate NA W xj L S Slide 23W. Rhett Davis NC State University ECE 546 Fall 2008 How many sides in the perimeter? Bottom Side wall Side wall Channel Source ND Channel-stop implant NA1 Substrate NA W xj L S Do we consider this side when calculating perimeter? Slide 24W. Rhett Davis NC State University ECE 546 Fall 2008 Junction Capacitance Slide 29W. Rhett Davis NC State University ECE 546 Fall 2008 How to find AS, AD, PS, & PD? Need to refer to the Layout! Slide 30W. Rhett Davis NC State University ECE 546 Fall 2008 Today’s Lecture Measuring Power/Energy in SPICE (5.5.4) Parasitic Capacitances (3.2.3, 3.3) Processing Technology & Layout (2.2-2.3) Slide 31W. Rhett Davis NC State University ECE 546 Fall 2008 Inverter Layout The following slides go over the layers and some of the design-rules for an inverter layout. Slide 32W. Rhett Davis NC State University ECE 546 Fall 2008 Classic CMOS Process Slide 33W. Rhett Davis NC State University ECE 546 Fall 2008 Modern CMOS Process p-well n-well p+ p-epi SiO2 AlCu poly n+ SiO2 p+ gate-oxide Tungsten TiSi2 Slide 34W. Rhett Davis NC State University ECE 546 Fall 2008 CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers Slide 39W. Rhett Davis NC State University ECE 546 Fall 2008 Threshold-Adjust Layers Modifier for an nwell or pwell Must be coincident with well shape “G” or “H” indicates general- or high- threshold Slide 40W. Rhett Davis NC State University ECE 546 Fall 2008 Poly-Silicon Layer (g) After polysilicon deposition and etch poly(silicon) Slide 41W. Rhett Davis NC State University ECE 546 Fall 2008 Active & Implant Layers nimplant in green pimplant in brown triangle fill-pattern to distinguish from active p+n+ (h) After n+ source/drain and p+source/drain implants. These steps also dope the polysilicon. Slide 42W. Rhett Davis NC State University ECE 546 Fall 2008 Metal1 and Contact Layers (i) After deposition of SiO2insulator and contact hole etch. SiO2 (j) After deposition and patterning of first Al layer. Al Slide 43W. Rhett Davis NC State University ECE 546 Fall 2008 P-Cells and Vias NTAP pmos_vtl M1_P nmos_vtl PTAP P-cells combine shapes from multiple layers Much more convenient than drawing layers individually Slide 44W. Rhett Davis NC State University ECE 546 Fall 2008 Identify the following nodes: Gate Source Drain Bulk