memory configuration - Microcomputer Applications - Exam, Exams of Microcomputers

Download memory configuration - Microcomputer Applications - Exam and more Exams Microcomputers in PDF only on Docsity! CORK INSTITUTE OF TECHNOLOGY INSTITIÚID TEICNEOLAÍOCHTA CHORCAÍ Semester 1 Examinations 2012/13 Module Title: Microcomputer Applications 590 Module Code: ELTR7029 School: Mechanical, Electrical & Process Engineering Programme Title: Bachelor of Engineering (Hons) in Electronic Systems Engineering Programme Code: EELES_8_Y3 External Examiner(s): Mr Traoloch O’Brien, Mr Ian Kennedy Internal Examiner(s): Mr F. O’Reilly Instructions: Answer 3 Questions. All questions carry equal marks. Duration: 2 Hours Sitting: Winter 2012/13 Requirements for this examination: Note to Candidates: Please check the Programme Title and the Module Title to ensure that you have received the correct examination paper. If in doubt please contact an Invigilator. Q1 (a) Microprocessors have been around since the 1970s, yet micro-controllers in their applications are relatively new, the last 10 or 15 years. Why have micro-controller evolved from microprocesors? What specific features do they have that makes them different from micro-processors? [9 marks] (b) You have the following selection of micro-processors/micro-controllers available to you for a number of projects: (i) Atmel AVR 8 bit micro-controller, 4 MHz (ii) Intel Atom Processor, x86/PC compatible microprocessor, 1.5GHz (iii) Microchip PIC 18f452 micro-controller 10MHz (iv) ARM 7 based 32 bit micro-controller (50MHz) Outline 4 categories/requirements you would examine each application under to determine its need for a micro-processor or micro-controller. [8 marks] Then for each of the following application choose one and justify why it is appropriate to that application.  Digital Camera with rapid image compression & multishot mode.  Untrasonic measuring unit which displays on a small screen.  Tablet/pocket computer which can run MS-Windows. [9 marks] (c) Describe your understanding of the memory configuration and usage in the PIC18f452 micro-controller. You should discuss how the program memory is organised and how the data memory is organised and what is kept in each part or memory. [8 marks] [Total: 34 marks] PIC18FXX2 TABLE 4-1: SPECIAL FUNCTION REGISTER MAP Address: ‘Name Address: Name ‘Address Name Address: Name FFFh TOSU FOFh | INDF2@) | FeFh [ CCPRIH FOFh FFER TOsH FDEn [| POSTINGZ®T | FBEh [_COPRAL FOEn FFDh TOSL FDDh | POSTDECZ™ FEDh | CCFICON FoDh FFch [__STKPTA FDCh | PREINCZ®! | FBCh | CCPAZH Fach FrBh | POLATU Foen | PLUSW2"7 Feeh | COPR2L FOBh FFAn | PCLATH FDAh | FSR2H FeAn | CCP2CON FoAh FFSh PCL Fooh | FSR2L FBh = FO9h FR&h TBLPTRU FO@h STATUS FB8h _- F98h FFTh [_TELPTRH FoTh | TMROH FB7h = FOTh FR6h TBLPTAL FOD6h TMROL FB6h _- FO6h FRFSh TABLAT FDSh TOCON FBSh _- FOSh Fah PRODH FDah = Fah = Foah FF3h PRODL FOSh OSCCON FB3h _TMASH 93h FF2h [__INTCON Fo2h | LVDCON Fe2h | TMRSL Fo2h FFth [_INTOON2 Foth | WDTCON Feith | TSCON Foth FFOn [_INTCONS Foon [CON FB0h = FO0h FeFh | _INDFOS FOFn | TMRIH FAFh| _ SPERG FBFh FEEh [ POSTINCOGT Fceh | TMAIL FAEn | _ACREG FaEh Feph | POSTDECO™ FeDh | TiCON FADh | TXREG F8Dh Fech | PREINCOP) FOCh TMR2 Fach | TXSTA FBCh FEBh PLUSWORT FCBh PR2 FABh ACSTA FSBh FEA FSROH FCAh T2CON AAR _- FaAh FESh FSAOL FC9h ‘SSPSUF FASH EEADA Fe9h FE8h WAEG FC8h ‘SSPADD FA8h EEDATA FS8h FeTh [_INDFI@? FoTh | SSPSTAT FATH FaTh FE6h POSTINGI@ FC6h SSPCON1 FAGh EECONt F86h Fesh [ POSTDECT™) Fosh | SSPCON2 FASh = FBSh Fedh [ PREINCIE? Fodh | ADRESH FAah = Fedh Fen [ PLUSWI? Fosh | ADRESL FA3h = FE3h Fen | FSRIH Fo2h | ADCONO FAH IPR Fah Feth| FSRAL Fcth | ADCONt FAth PIR2 Fath FEOh BSR FCOh _ FAOh PIE2 Fe0h Note 4: Unimplemented registers are read as ‘U’. 2 This register is not available on PIC18F2X? devices. 3: This is nota physical register. TABLE 16-1; BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC(64(X+1)) Baud Rate = FOSc/(16(X+1)) 2 (Synchronous) Baud Rate = Fosci(4(X+1)) NA Legend: X = value in SPBRG (0 to 255) TABLE 16-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR on ‘Value on Name | Bit7 | Bits | Bits | Bit4 | Bits | Bit2 | Bitt | Bito | Loo 'EoR | All Other * RESETS TXSTA CSAC | TX9 | TXEN | SYNC = BAGH | TRMT | TX9D | oo00 -010 | oo90 -o10 RCSTA SPEN | AX9 | SREN | CREN | ADDEN | FERR | OERR | RX9D | o1 -o0x | 0000 -oox SPBRG [Baud Rate Generator Register 000 0000 000 0000 Legend: x = unknown, - = implemented, read as ‘0’. Shaded cells are not used by the BRG. REGISTER 17-1: ADCONO REGISTER REGISTER 17-2: ADCON1 REGISTER RW0 RWO RWO RW0 RWO AWO U0 RW mo MORRO Abost |.Apos0 | “oHs2'_| (GHet | _GH50_| GO/DONE [EEEemmal -ADON (sor anos [= ras | rorae | Foret | Pcre0 | D7 Dito aT ta bit7-6 | ADCS1:ADCSO: A/D Conversion Clock Select bits (ADCONO bits in bold) bit ADEM A/D Result Format Setect bit 11 = Right usified_ Six (6) Most Significant bits of ADRESH are read a5 0 7pcont | ADGONO (0 = Left ustiied. Sex (@) Least Signsicant ite of ADRESL are rad ae <A0c82; | <aDost:ADCSo> ‘Clock Conversion bit ADES2: AD Conversion Glock Select bt (ADCON bits in bel) 00 or, 20 "DCONT | _ADCONT <ADCS2> | <ADCS1:ADCSO> o Fone (Clock Conversion ar 00, on. 10 FOSCIe4 a AG (Glock derived from the intemal osclator) bitS-3 CHS2:CHSO: Analog Channel Select bits ‘000 = channel 0, (ANO) ee | oe | ane | ane] ane | ama | ane | ant | ano] veces | vier] cre A war pA pa] Ap A [wes[ a DADA [we [wee 211 = channel 7, (AN7) ome[ op po pofal a | Aa [A] A | voo | ves | 570 Note: The PIC18F2X2 devices do not implement the full 8 A/D channels; the unimplemented oor {| 0 | pf of A |Weref A [A | A | ase | ves | ait selections are reserved. Do not select any unimplemented channel. HE SES — waxfofoelfoefe|o fo folol—|—|ow bR2 = GOIDONE: A/D Conversion Status bit noo [apa | a | «| wes [ver [a [a [me | aw | oz ‘When ADON = 1: aon [ofofala A A [AT A | woo | wes [670 = A/D conversion in progress (setting this bit starts the A/D conversion which is automatically wee po pe papa pwr [oa pa ba pae ves [sr cleared by hardware when the A/D conversion is complete) se Dee a ee De ee 0 = AD conversion not in progress aaoo | 0 fo | 0 | a | were | wee | A | A | ANS [ AN | aD bit1 __Unimplemented: Read as 0 mao [0 fo | 0 | 0 | ware [we [a | a | ma | ane | 22 bito — ADON: A/D On bit m= po pe }o),e) o | 0 [o) A] ve | we | 0 10 cairo procs powered ty apo po] os |. |wes [wer po pA we [awe | ve D converter module is shut-off and consumes no operating current Anaioginput_D= Digital jal VO input channels /# of AD valage references: I i