Memory Hierarchy and Cache Systems in CPSC 440, Study notes of Computer Architecture and Organization

Download Memory Hierarchy and Cache Systems in CPSC 440 and more Study notes Computer Architecture and Organization in PDF only on Docsity! CPSC 440, Dr. Wang 1 CPSC 440 Lecture 5 The Memory Hierarchy 1) Memory technology: faster => more expensive. 2) The principle of locality: temporal locality (e.g. loop code), spatial locality (e.g. array, sequential code). 1 + 2 => memory hierarchy For each level: 1) Hit: when the requested data is present. 2) Miss: when the requested data is absent. 3) Hit time: the time to look for the item + the time to read that item. 4) Miss penalty: the time to get the item from the lower level + the time to deliver the block to the processor. 5) Miss time*: the time to look for the item + miss penalty. 6) Hit rate (hit ratio): number of hits / total accesses. 7) Miss rate: number of misses / total accesses = 1 – hit rate. CPSC 440, Dr. Wang 2 The Basics of Cache 1. A simple placement policy: direct mapping. Cache Index = (Block Address) Modulo (Number of Block in the Cache) e.g. e.g. see page 460 and 461. Valid bit: indicates whether the current cache block is valid. Tags: distinguish different memory blocks that can get into the same cache block. = 10 Byte offset V Tag Data(32bits) 10 Index20 Tag 32 Data hit? 20 What is the total number of bits needed to implement the cache? Total number of bits = Number of entries * (Valid + Tag + Data) Tag(bits) = Address(bits) – Index(bits) – 2(Byte offset) = 32 - n – 2 = 30 - n Assume we have 2n entries, one word block. Total number of bits = 2n *( 1 + 30 – n + 32) = 2n *( 63 – n ) Assume 4 KB Cache, n=10. Total number of bits = 53 Kbits.