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Memory Hierarchy Designer’s Concerns-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture

This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: Memory, Hierarchy, Designer, Performance, Enhancemen, strategy, Cache, Pollicies, Block, Placement

Typology: Slides

2011/2012

Uploaded on 08/06/2012

amrusha
amrusha 🇮🇳

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Download Memory Hierarchy Designer’s Concerns-Advance Computer Architecture-Lecture Slides and more Slides Advanced Computer Architecture in PDF only on Docsity! Today’s Topics Recap: Cache Addressing Techniques Placement and Replacement Policies Cache Write Strategy Cache Performance Enhancement Summary docsity.com Recap: Block Size Trade off Impact of block size on the cache performance and categories of cache design The trade-off of the block size verses the Miss rate, Miss Penalty, and Average access time , the basic CPU performance matrices docsity.com Recap: Cache Organizations – Direct Mapped where each block has only one place it can appear in the cache – Conflict Miss – Fully Associative Mapped where any block of the main memory can be placed any where in the cache; and – Set Associative Mapped which allows to place a block in a set of places in the cache docsity.com Memory Hierarchy Designer’s Concerns Block placement: Where can a block be placed in the upper level? Block identification: How is a block found if it is in the upper level? Block replacement: Which block should be replaced on a miss? Write strategy: What happens on a write? docsity.com Block Placement Policy Fully Associative: Block can be placed any where in the upper level (Cache) E.g. Block 12 from the main memory can be place at block 2, 6 or any of the 8 block locations in cache docsity.com Block Identification How is a block found if it is in the upper level? Tag/Block A TAG is associated with each block frame The TAG gives the block address All possible TAGS, where a block may be placed are checked in parallel Valid bit is used to identify whether the block contains correct data –No need to check index or block offset docsity.com Block Identification: Direct Mapped Cache Index 5bits 0 1 Cache Data Byte 0 0 4 31 Cache Tag (22-bits) Ex: 0x00 22 bit Valid Bit Byte 1 Byte 31 : Byte 32 Byte 33 Byte 63 : Cache Tag Byte Select Ex: 0x00 9 31 Lower Level (Main) memory: 4GB – 32-bit address 31 docsity.com Block Identification Cache Index 4bits 0 4 31 Cache Tag (23-bits) Byte Select 8 9 0 1 Byte 0 Byte 1 Byte 31 : Byte 32 Byte 33 Byte 63 : 15 0 1 Byte 0 Byte 1 Byte 31 : Byte 32 Byte 33 Byte 63 : 15 23bit 23bit docsity.com
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