Memory Latches and Registers - Lecture Slides | COMP 411, Study notes of Computer Architecture and Organization

Download Memory Latches and Registers - Lecture Slides | COMP 411 and more Study notes Computer Architecture and Organization in PDF only on Docsity! L13 – Memory 1Comp 411 – Fall 2006 10/16/06 Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 – Memory 2Comp 411 – Fall 2006 10/16/06 General Table Lookup Synthesis MUX Logic A B Fn(A,B) Generalizing: Remember from a few lectures ago that, in theory, we can build any 1-output combinational logic block with multiplexers. For an N-input function we need a _____ input multiplexer. BIG Multiplexers? How about 10-input function? 20-input? AB Fn(A,B) 00 0 01 1 10 1 11 0 2N L13 – Memory 5Comp 411 – Fall 2006 10/16/06 Shared Decoding Logic 0 2 3 4 5 6 71 A B Cin S Cout There’s an extra level of inversion that isn’t necessary in the logic. However, it reduces the capacitive load on the module driving this one. These are just “DeMorgan”ized NOR gates Made from PREWIRED connections , and CONFIGURABLE connections that can be either connected or not connected We can build a general purpose “table-lookup” device called a Read-Only Memory (ROM), from which we can implement any truth table and, thus, any combinational device Decoder Configurable Selector This ROM stores 16 bits in 8 words of 2 bits. L13 – Memory 6Comp 411 – Fall 2006 10/16/06 ROM Implementation Details Hardwired “AND” logic Programmable “OR” logic Advantages: - Very regular design (can be entirely automated) Problems: - Active Pull-ups (Static Power) - Long metal runs (Large Caps) - Slow A B Cin S Cout JARGON: Inputs to a ROM are called ADDRESSES. The decoder’s outputs are called WORD LINES, and the outputs lines of the selector are called BIT LINES. Tiny PFETs with gates tied to ground = resistor pullup that makes wire “1” unless one of the NFET pulldowns is on. Decoder Values: 0 1 2 3 4 5 6 7 A “word”-line. A “bit”-line These transistors are function “dependent” These transistors implement a decoder, and are independent of function. L13 – Memory 7Comp 411 – Fall 2006 10/16/06 Logic According to ROMs ROMs ignore the structure of combinational functions ... • Size, layout, and design are independent of function • Any Truth table can be “programmed” by minor reconfiguration: - Metal layer (masked ROMs) - Fuses (Field-programmable PROMs) - Charge on floating gates (EPROMs) ... etc. Model: LOOK UP value of function in truth table... Inputs: “ADDRESS” of a T.T. entry ROM SIZE = # TT entries... ... for an N-input boolean function, size = __________2N x #outputs L13 – Memory 10Comp 411 – Fall 2006 10/16/06 A Simple ROM implementation A B C T/Z U/Y V/X W 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 A B C T/Z U/Y V/X W That was Easy! ROMs are even more flexible than MUXes, because you can design the H/W first, and figure out the logic later! This is the essence of programability: “LATE-BINDING” logic specification. T V X U Y Z W Decoder Values: 0 1 2 3 4 5 6 7 L13 – Memory 11Comp 411 – Fall 2006 10/16/06 “Programmable” Look-up Tables REMEMBER, every combinational circuit can be expressed as a lookup table. As a result a ROM is a universal logic device. Unfortunately, the ROMs we’ve built thus far are “HARDWIRED”. That is, the function that they compute is encoded by the pull-down transistors that are built into the OR-plane of the ROM. What we’d really like is a combinational gate that could be reconfigured dynamically. For this we’ll need some form of storage. The function of a ROM is determined by the presence of a transistor at the intersection of a WORD line from the AND array with a BIT line going to the OR array WORD line BIT line How to “store” a “bit”? L13 – Memory 12Comp 411 – Fall 2006 10/16/06 Analog Storage: Using Capacitors We’ve chosen to encode information using voltages and we know from physics that we can “store” a voltage as “charge” on a capacitor: bit line N-channel FET serves as an access switch VREF Pros:
compact! Cons:
it leaks! ⇒ refresh
complex interface
reading a bit, destroys it (you have to rewrite the value after each read)
it’s NOT a digital circuit To write: Drive bit line, turn on access fet, force storage cap to new voltage To read: precharge bit line, turn on access fet, detect (small) change in bit line voltage word line This storage circuit is the basis for commodity DRAMs L13 – Memory 15Comp 411 – Fall 2006 10/16/06 Looking Under the Covers Let’s take a quick look at the equivalent circuit for our MUX when the gate is LOW (the feedback path is active) D G=0 Q Q G=0 D 0 1 1 1 Q This storage circuit is the basis for commodity SRAMs Advantages: 1) Maintains remembered state for as long as power is applied. 2) State is DIGITAL Disadvantage: 1) Requires more transistors L13 – Memory 16Comp 411 – Fall 2006 10/16/06 Why Does Feedback = Storage? BIG IDEA: use positive feedback to maintain storage indefinitely. Our logic gates are built to restore marginal signal levels, so noise shouldn’t be a problem! VIN VOUT Result: a bistable storage element Feedback constraint: VIN = VOUT VTC for inverter pair VIN VOUT Three solutions:
two end-points are stable
middle point is unstable Not affected by noise We’ll get back to this! L13 – Memory 17Comp 411 – Fall 2006 10/16/06 Static D Latch G D Q D G Q stable Q follows D Positive latch Q “static” means latch will hold data (i.e., value of Q) while G is inactive, however long that may be. G D Q Negative latch Q G D 1 0 What is the difference? L13 – Memory 20Comp 411 – Fall 2006 10/16/06 Flakey Control Systems Here’s a strategy for saving 2 bucks the next time you find yourself at a toll booth! L13 – Memory 23Comp 411 – Fall 2006 10/16/06 Escapement Strategy The Solution: Add two gates and only open one at a time. L13 – Memory 38Comp 411 – Fall 2006 10/16/06 Escapement Strategy The Solution: Add two gates and only open one at a time. (Psst… Don’t tell the toll folks) KEY: At no time is there an open path through both gates… L13 – Memory 41Comp 411 – Fall 2006 10/16/06 Two Issues G D Q G D QD Q master slave CLK • Must allow time for the input’s value to propagate to the Master’s output while CLK is LOW. • This is called “SET-UP” time • Must keep the input stable, just after CLK transitions to HIGH. This is insurance in case the SLAVE’s gate opens just before the MASTER’s gate closes. • This is called “HOLD-TIME” • Can be zero (or even negative!) • Assuring “set-up” and “hold” times is what limits a computer’s performance L13 – Memory 42Comp 411 – Fall 2006 10/16/06 Flip-Flop Timing Specs CLK D Q D QD CLK Q <tPD tPD: maximum propagation delay, CLK →Q >tSETUP tSETUP: setup time guarantee that D has propagated through feedback path before master closes >tHOLD tHOLD: hold time guarantee master is closed and data is stable before allowing D to change L13 – Memory 43Comp 411 – Fall 2006 10/16/06 Summary • Regular Arrays can be used to implement arbitrary logic functions • ROMs decode every input combination (fixed-AND array) and compute the output for it (customized-OR array) • PLAs decode an minimal set of input combinations (both AND and OR arrays customized) • Memories • ROMs are HARDWIRED memories • RAMs include storage elements at each WORD-line and BIT-line intersection • dynamic memory: compact, only reliable short-term • static memory: controlled use of positive feedback • Level-sensitive D-latches for static storage • Dynamic discipline (setup and hold times)