Memory Operations in Computer Architecture | CSCI 4717, Study Guides, Projects, Research of Computer Architecture and Organization

Download Memory Operations in Computer Architecture | CSCI 4717 and more Study Guides, Projects, Research Computer Architecture and Organization in PDF only on Docsity! CSCI 4717 – Computer Architecture Project 1: Two-Stage Instuction Decoder Due: Monday, September 21, 2006 at 11:59 PM What to submit: You will be submitting a text file containing two C functions, fetchNextInstruction() and executeInstruction(). Submit your project using the digital dropbox on Blackboard. The steps below should help you if you have never used this feature of Blackboard before: 1. Begin by clicking on "Tools" and selecting "Digital Dropbox". 2. In the window that appears, click on the "Send file" button to send your C sourcecode file to me. 3. In some cases, a scrollbox will appear under the heading "Select Users". If this happens, highlight my name from the list. 4. Be sure to name your file decoder _username where your z-account name is substituted for the word "username". 5. Use the "Browse" button to retrieve your file from the hard drive. 6. Click "Submit" to send me the file. By using the "Add file" button, you will not be submitting your work to me, only uploading it to your account on Blackboard. I am sorry, but I will have to consider it late if you do not actually send me the file. I will try to notify you when I receive your file. Introduction This assignment is to design a simple processor based on the simplified 2-step instruction cycle shown in Figure 3.3 of our textbook. You will be creating two functions in software, one to simulate the fetch next instruction cycle, fetchNextInstruction(), and one to simulate the execute instruction cycle, executeInstruction(). Neither of these functions will have parameters nor will they return values. They will operation on global data meant to simulate the registers and memory of the processor. This simulated machine consists of four registers that will be represented in your software with four global variables. • PC -- Program counter (16 bit) used to hold the address of the next instruction to execute. It is initialized to zero. • IR -- Instruction register (8 bit) used to hold the current instruction being executed • MAR -- Memory Address Register (16 bit) used to hold an address being used as a pointer, i.e., an indirect reference to data in memory • ACC -- Accumulator (8 bit) used to operate on data Memory will be simulated with an array memory[65536]. The function fetchNextInstruction() will perform the following steps: • Use the program counter (PC) as an index to retrieve an instruction from the array memory[]. • Store the retrieved instruction to the instruction register (IR). • Determine from the instruction how much to increment PC so that it points to the next instruction in memory[] and perform the increment. The function executeInstruction() will examine IR to determine which operation to perform and it will perform it on the data contained in the registers and in the array memory[]. CSCI 4717 Project 1 Page 2 Instruction (Opcode) Set The following is a break down of the opcodes of the simple machine for which you are designing a simulator. The data (operands) for each instruction will follow the opcode immediately in memory. It is important to note that when using a16-bit operand (data or memory address), the byte immediately following the opcode is the most significant byte of the address and the byte following that is the least significant. This is referred to as "Big Endian". The opcode for this machine will always be 8 bits. This means that the size of an instruction along with its data could be 1 byte (an opcode that doesn't need an operand), 2 bytes (an opcode that uses 8-bit immediate data, i.e., a constant), or 3 bytes (an opcode that uses an address as its operand or 16-bit immediate data). Mathematical Operations: If the most significant bit of the opcode is 1, then the opcode represents a mathematical function. The opcode may be followed by 0, 1, or 2 bytes of operands. * -- The constant is passed to the processor as an 8- or 16-bit operand following the opcode ** -- The memory address is passed to the processor as a 16-bit operand following the opcode 1 Source: 00 – Indirect (MAR used as pointer) 01 – Accumulator ACC 10 – Constant* 11 – Memory** Destination: 00 – Indirect (MAR used as a pointer) 01 – Accumulator ACC 10 – Address register MAR 11 – Memory** Function: 000 – AND 001 – OR 010 – XOR 011 – ADD 100 – SUB 101 – INC 110 – DEC 111 – NOT OPCODE OPCODE IMMED. DATA 8 bits 16 bits OPCODE DATA (MSB) 24 bits DATA (LSB) OPCODE ADDRESS (MSB) 24 bits ADDRESS (LSB)