Download Exam Questions: Computer Architecture for Software Dev & Networking Students, 68000 Proces and more Exams Computer Architecture and Organization in PDF only on Docsity! Cork Institute of Technology Bachelor of Science (Honours) in Software Development & Computer Networking – Stage 2 (Bachelor of Science in Software Development & Computer Networking – Stage 2) (NFQ – Level 8) Autumn 2005 COMPUTER ARCHITECTURE (Time: 3 Hours) Answer any four questions. Examiner: Mr. S. Lankford Dr. D. Chambers Mr. E. A. Parslow Mr. P. O’Connor Q1 (a) With appropriate diagrams, illustrate and explain the operation of the stack in the 68000 processor. In your explanation, use either RTL or sample code, to illustrate the push and pull stack operations. (10 marks) (b) Explain and Illustrate, where necessary, what effect the following code samples have on the stack: (i) MOVE.W 4(A7),D2 (ii) MOVE.L (A7)+,D4 (iii) LEA $4000, A7 (6 marks) (c) Given the following DATA section: ORG DATA X DS.B 1 Write a subroutine, to evaluate x7. The value of x is passed to the subroutine via the stack. Write a 68000 program, which uses this subroutine to evaluate the following expression: (3x7 +8) 7x7 The subroutine is to return the result of the calculation via the stack and then store the answer in D6. It is assumed that, once the program is loaded, the value X = 4 is copied into memory using the memory viewer. (9 marks) [Total 25 marks] 2 Q2. (a) Explain the operation of memory mapped IO in the 68000 microprocessor. (3 marks) (b) Illustrate a typical circuit that could be used to implement an 8-bit memory mapped input and output port. Briefly describe its operation. (6 marks) (c) Briefly explain the function of the 68230 PI/T in a 68000 microprocessor-based system. (4 marks) (d) Illustrate how the 68230 is interfaced with a 68000-based system. Clearly label all pins and explain how the arrangement works. Identify the type of data transfer, and the signals used to implement data transfer, between the 68230 and the 68000. (12 marks) [Total 25 marks] Q3. (a) Briefly explain what is meant by a vectored interrupt. (3 marks) (b) Briefly explain and illustrate how interrupt requests can be prioritised using daisy chaining. (7 marks) (c) Using a diagram of the 68000 processor, illustrate and explain how a level 6 vectored interrupt is responded to. In your diagram, show the appropriate pins on the 68000, the IRQ and IACK lines, encoders/decoders and any interface logic that is required. (10 marks) (d) Using a Bus Arbitration Cycle flowchart, show how an external device requests the bus of the 68000 processor. In your flowchart, clearly outline the microprocessor signals which are required. (5 marks) [Total 25 marks]
