Midterm 1 Study Guide | Computer Architecture | EEL 5764, Exams of Computer Architecture and Organization

Download Midterm 1 Study Guide | Computer Architecture | EEL 5764 and more Exams Computer Architecture and Organization in PDF only on Docsity! Midterm 1 Study Guide Chapter 1 – Fundamentals of Computer Design • Different goals for different classes of computers • Discuss the power wall, ILP wall and memory wall and the implications of each • Why has multicore technology become so important? • In optimizations, why is it important to focus on the common case? • Trends in technology o Integrated circuit logic technology - Moore’s law o Performance trends – Bandwidth over Latency o Trends in power  Clock gating  Static power vs. dynamic power • Dependability o Mean time to failure (MTTF)  Why is this misleading? o Mean time between failures (MTBF) o Module availability o Problem similar to the example on page 26 o Problem similar to the example on page 27 o Why is a single point of failure bad? • Measuring, reporting and summarizing performance o Comparing two systems, showing speedup  Equations on page 28 o Throughput o How do you define time for comparisons? o Benchmarks  Why are benchmarks important?  Why do benchmarks need multiple applications?  Why is it important to run the entire benchmark suite and not a subset?  Why is it necessary to create new benchmark suites? • Quantitative principles of computer design o Amdahl’s Law  Define  Use  Why is Amdahl’s law fundamental to system design?  Problems similar to those on pages 40-41 o Processor performance equation  Calculate CPU time  Calculate CPI  What are the components of CPI?  Problem similar to the one on page 43 Appendix A – Pipelining: Basic and Intermediate Concepts • What is pipelining? • What is parallelism? • How does pipelining exploit parallelism? • What are the advantages and disadvantages of a deeper pipeline? • What is a RISC machine (and I don’t just want the acronym) o In terms of types of instructions and structure of instructions • Why is a RISC machine easy to pipeline and a CISC machine more difficult? • What are the 5 pipeline stages? What happens in each stage? • How can the register file be used in two pipeline stages? • What is the purpose of pipeline registers? What information do they hold? Why are they essential to pipelining? • The major hurdle of pipelining – pipeline hazards o What are the 3 pipeline hazards? o Why must a pipeline stall? o What is the difference between a data dependency and a data hazard?  Give code that shows a both data dependencies and data hazards and identify both o Show how pipeline stalls can effect the CPI  Equations on page A-12  Exercise on page A-13 o Identify potential structural hazards in the standard 5 stage MIPS pipeline. How are these hazards avoided? o What mechanisms exist for minimizing stalls due to data hazards?  Show the flow of data as in figures A.7 and A.8  Which data hazards always results in a stall? Give an example in assembly. How can this stall be avoided. o Branch/control hazards?  What are they?  Why are they such a problem in pipelining  What mechanisms exist for reducing the effects of branch hazards? What are each of the following and discuss advantages/disadvantages • Stall then flush pipeline if necessary • Predicted not taken • predicted taken • Delayed branch o What is a branch delay slot? How is it filled (3 possibilities)? Appendix C • The 36 terms on page C-2 • What are the 3 C’s in cache misses? What causes them and how can they be reduced/avoided? • The 4 memory hierarchy questions on page C-6 • Calculate average memory access time as in the example on page C-15 and C-16, C-26, C-31, 295, • 6 Basic cache optimizations – what are they and how do they improve cache performance? Do they always improve performance or does it depend on the benchmark? • larger block size to reduce miss rate • Larger caches to reduce miss rate • Higher associativity to reduce miss rate • Multilevel caches to reduce miss rate • Giving priority to read misses over writes to reduce miss penalty • Avoiding address translation during indexing of the cache to reduce hit time • Virtual memory • What is it? • What is its purpose? • How does it help a program? How does it hurt a program? • What does it mean to have a cache that is virtually indexed virtually tagged or virtually indexed physically tagged? What are the advantages and/or disadvantages of either way • What are page tables and what do they mean for virtual memory? • How can you speed up address translation? Chapter 2 – Instruction-Level Parallelism and Its Exploitation • What is ILP? o How does pipelining exploit ILP? Why is the pipeline essential to exploit ILP? • Why is speculation imperative to exploiting more ILP? • What is a data dependency? • What is a name dependency? o Why are there name dependencies and how can we overcome them? • What is a control dependency? • Data hazards o What are the three types of hazards? o Give an example of each with assembly code • Basic compiler techniques for exposing ILP? o Pipeline scheduling and loop unrolling o Example on page 76 o Example on page 77 o Example on page 78 o Slides 17-22, you might have to do something similar o Why is loop unrolling hard? What things must be considered? What fundamental requirements in loop structure are necessary to fully exploit loop unrolling?  Register pressure