Midterm Exam 2 - Computer Architecture II: Hardware-Software Interface | CS 366, Exams of Computer Architecture and Organization

Download Midterm Exam 2 - Computer Architecture II: Hardware-Software Interface | CS 366 and more Exams Computer Architecture and Organization in PDF only on Docsity! CS 366 - Computer Architecture II, Midterm Exam #2, page 1 of 6 CS 366 - Computer Architecture II Midterm Exam #2 - Prof. Reed Fall 2003 What is your name?: ___________________________(0 points) There are two sections: I. Short Questions . . . . . . . . .20 points; (10 questions, 2 points each) II. Short Sections of Code . . .80 points; (10 questions, 8 points each) --------------- 100 points total This test is worth 20% of your final grade. This test is open book and open notes. You have 75 minutes. I. True/False: (2 pts. each) T F 1. There is at least one MIPS assembler instruction that can directly store a result of an ALU calculation into memory. T F 2. In addition to the 32 MIPS register file registers having mnemonic names such as $t3, the registers can be referred to by their number, starting from $1 up to and including $32. T F 3. Usage conventions for register use (what registers are used for what purposes) are strictly enforced by the assembler. T F 4. The value part (in this case 0xffff) of the instruction li $t3, 0xffff can actually be a 32-bit value. T F 5. In the IEEE 754 single precision floating-point format, just like in mathematics, any number to the 0th power is 1. T F 6. Values for IEEE 754 single precision floating-point format numbers are unevenly distributed between the largest and smallest possible values. T F 7. Choosing a format to represent floating-point numbers involves a tradeoff between range of values that can be represented, and precision of numbers that can be represented. T F 8. Each state in an ASM diagram corresponds to one or more microprogram statements. T F 9. Once an IR is implemented in a control unit design, the MDR is only used to write to mem- ory, and all reading from memory is through the IR. T F 10. The format of the IR limits the number of registers that can be used concurrently, however a microprogram instruction could still write to all registers in a single instruction. CS 366 - Computer Architecture II, Midterm Exam #2, page 2 of 6 III. Short Answer: (8 points each) Where there are multiple steps, please circle your final answer. You must show your work for credit. 1. Consider the following instruction: or $a1,$t2,$t3 Write this instruction in hexadecimal. 2. Consider the following value, using the IEEE 754 single precision floating-point format. What is the equivalent value as a decimal number? 0100 0011 0101 0100 0000 0000 0000 0000 3. Convert the following decimal value into a denormalized IEEE 754 single precision floating-point for- mat. Write your answer in hexadecimal. -0.65625 4. Consider the following value, using the IEEE 754 single precision floating-point format. What is the equivalent value as a decimal number? 0111 1111 1011 0100 0000 0000 0000 0000 CS 366 - Computer Architecture II, Midterm Exam #2, page 5 of 6 9. Consider the microcode file given on the last page of this test. a. (4 points) Rewrite the memory file program shown below using assembler-like sytnax (e.g. r2 <- r2 - r1 ). Write each assembler-like statement next to the corresponding line(s). b. (4 points) What is the final value stored in register 0 after this memory file program is run? Please circle your answer. 10. Consider the microcode file given on the last page of this test. What does opcode 12 do? Memory file % 0: 00001010 1: 00001000 2: 00000000 3: 00100100 CS 366 - Computer Architecture II, Midterm Exam #2, page 6 of 6 // ucode file fetch0: a_sel=7, b_sel=7, alu_sel=AND, r6_write, mar_sel=LOAD; fetch1: r7_write, a_sel=6, alu_sel=ADDA, c_in, read, ir0_sel=LOAD, if wait then goto fetch1 endif; fetch2: a_sel=7, b_sel=7, alu_sel=AND, r6_write, mar_sel=LOAD; fetch3: r7_write, a_sel=6, alu_sel=ADDA, c_in, read, ir1_sel=LOAD, if wait then goto fetch3 endif; goto opcode[IR_OPCODE]; opcode[0]: goto fetch0; // 0) NO_OP opcode[1]: ri_sel, rj_sel, rk_sel, alu_sel=ADD, goto fetch0; // 1) ADD (ri <- rj + rk) opcode[2]: result_sel=IR_CONST8, ri_sel, goto fetch0; // 2) LOAD_IMMEDIATE (ri <- ir_const4) opcode[3]: rj_sel, alu_sel=SUBA, r6_write, result_sel=IR_CONST4, // 3) BR_IF_ZERO (bz rj, ir_const4) if c_out then goto fetch0 else goto branch endif; opcode[4]: rj_sel, alu_sel=SUBA, r6_write, result_sel=IR_CONST4, // 4) BR_IF_NOT_ZERO (bnz rj, ir_const4) if c_out then goto branch else goto fetch0 endif; opcode[5]: a_sel=0, b_sel=0, alu_sel=AND, r6_write, result_sel=IR_CONST8, goto branch; // 5) JUMP (jump ir_const8) opcode[6]: ri_sel, rj_sel, alu_sel=ADDA, goto fetch0; // 6) MOVE (ri <- rj) opcode[7]: rj_sel, alu_sel=ADDA, mar_sel=LOAD, goto opcode7.1; // 7) STORE_BYTE (mem[rj] <= rk) opcode[8]: rj_sel, alu_sel=ADDA, mar_sel=LOAD, goto opcode8.1; // 8) LOAD_BYTE (ri <- mem[rj]) opcode[9]: rj_sel, r6_write, alu_sel=ADDA, goto opcode9.1; // 9) ? opcode[10]: ri_sel, rj_sel, rk_sel, c_in, alu_sel=SUB, goto fetch0; // 10) SUB (ri <- rj - rk) opcode[11]: goto opcode[11]; // 11) HALT opcode[12]: rj_sel, alu_sel=SUBA, r6_write, result_sel=IR_CONST4, if c_out then goto label_4 else goto branch endif; branch: r7_write, a_sel=7, b_sel=6, alu_sel=ADD, goto fetch0; opcode7.1: a_sel=5, b_sel=5, alu_sel=SUB, c_in, r5_write; rk_sel, a_sel=5, alu_sel=OR, mdr_sel=LOAD_ALU; memwrite: write, if wait then goto memwrite else goto fetch0 endif; opcode8.1: read, mdr_sel=LOAD_MEM, if wait then goto opcode8.1 endif; result_sel=MDR, ri_sel, goto fetch0; opcode9.1: r5_write, r4_write, a_sel=4, b_sel=4, alu_sel=SUB, c_in; r4_write, a_sel=4, b_sel = 4, alu_sel=ADD, c_in; r4_write, a_sel=4, b_sel = 4, alu_sel=ADD, c_in; r4_write, a_sel=4, b_sel = 4, alu_sel=ADD, c_in; loop: r4_write, a_sel=4, alu_sel=SUBA, if c_out then goto label_1 endif; ri_sel, a_sel=5, alu_sel=ADDA, goto fetch0; label_1: r6_write, a_sel=6, b_sel=6, alu_sel=ADD, if c_out then goto label_2 else goto label_3 endif; label_2: r5_write, a_sel=5, b_sel=5, alu_sel=ADD, c_in, goto loop; label_3: r5_write, a_sel=5, b_sel=5, alu_sel=ADD, goto loop; label_4: rj_sel, alu_sel=ADDA, r6_write, result_sel=IR_CONST4, if m_7 then goto branch else goto fetch0 endif; Microcode file used in Mythsim, for use with questions on this test. The microcode is very similar to that discussed in class. Differences are the addition of opcodes 4 (bnz) and "mystery" opcodes 9 & 12. For convenience you may want to tear off this sheet from the rest of the test. You do not need to turn in this sheet. CS 366 - Computer Architecture II, Midterm Exam #2, page 1 of 6 CS 366 - Computer Architecture II Midterm Exam #2 - Prof. Reed Fall 2003 What is your name?: ___________________________(0 points) There are two sections: I. Short Questions . . . . . . . . .20 points; (10 questions, 2 points each) II. Short Sections of Code . . .80 points; (10 questions, 8 points each) --------------- 100 points total This test is worth 20% of your final grade. This test is open book and open notes. You have 75 minutes. I. True/False: (2 pts. each) T F 1. There is at least one MIPS assembler instruction that can directly store a result of an ALU calculation into memory. T F 2. In addition to the 32 MIPS register file registers having mnemonic names such as $t3, the registers can be referred to by their number, starting from $1 up to and including $32. T F 3. Usage conventions for register use (what registers are used for what purposes) are strictly enforced by the assembler. T F 4. The value part (in this case 0xffff) of the instruction li $t3, 0xffff can actually be a 32-bit value. T F 5. In the IEEE 754 single precision floating-point format, just like in mathematics, any number to the 0th power is 1. T F 6. Values for IEEE 754 single precision floating-point format numbers are unevenly distributed between the largest and smallest possible values. T F 7. Choosing a format to represent floating-point numbers involves a tradeoff between range of values that can be represented, and precision of numbers that can be represented. T F 8. Each state in an ASM diagram corresponds to one or more microprogram statements. T F 9. Once an IR is implemented in a control unit design, the MDR is only used to write to mem- ory, and all reading from memory is through the IR. T F 10. The format of the IR limits the number of registers that can be used concurrently, however a microprogram instruction could still write to all registers in a single instruction. CS 366 - Computer Architecture II, Midterm Exam #2, page 4 of 6 8. Consider the microcode file given on the last page of this test. a. (4 points) Rewrite the memory file program shown below using assembler-like sytnax (e.g. r2 <- r2 - r1 ). Write each assembler-like statement next to the corresponding line(s). b. (4 points) What is the final value stored in register 0 after this memory file program is run? Please circle your answer. . Memory file % 0: 0 1: 000010 00 2: 2 3: 000010 01 4: 3 5: 000010 10 6: 1 7: 000010 11 8: 10 00 0110 9: 000011 00 10: 00 01 0000 11: 000001 00 12: 10 11 0000 13: 001010 10 14: 11111000 15: 000101 00 16: 0 17: 001011 00 CS 366 - Computer Architecture II, Midterm Exam #2, page 5 of 6 9. Consider the microcode file given on the last page of this test. a. (4 points) Rewrite the memory file program shown below using assembler-like sytnax (e.g. r2 <- r2 - r1 ). Write each assembler-like statement next to the corresponding line(s). b. (4 points) What is the final value stored in register 0 after this memory file program is run? Please circle your answer. 10. Consider the microcode file given on the last page of this test. What does opcode 12 do? Memory file % 0: 00001010 1: 00001000 2: 00000000 3: 00100100 CS 366 - Computer Architecture II, Midterm Exam #2, page 6 of 6 // ucode file fetch0: a_sel=7, b_sel=7, alu_sel=AND, r6_write, mar_sel=LOAD; fetch1: r7_write, a_sel=6, alu_sel=ADDA, c_in, read, ir0_sel=LOAD, if wait then goto fetch1 endif; fetch2: a_sel=7, b_sel=7, alu_sel=AND, r6_write, mar_sel=LOAD; fetch3: r7_write, a_sel=6, alu_sel=ADDA, c_in, read, ir1_sel=LOAD, if wait then goto fetch3 endif; goto opcode[IR_OPCODE]; opcode[0]: goto fetch0; // 0) NO_OP opcode[1]: ri_sel, rj_sel, rk_sel, alu_sel=ADD, goto fetch0; // 1) ADD (ri <- rj + rk) opcode[2]: result_sel=IR_CONST8, ri_sel, goto fetch0; // 2) LOAD_IMMEDIATE (ri <- ir_const4) opcode[3]: rj_sel, alu_sel=SUBA, r6_write, result_sel=IR_CONST4, // 3) BR_IF_ZERO (bz rj, ir_const4) if c_out then goto fetch0 else goto branch endif; opcode[4]: rj_sel, alu_sel=SUBA, r6_write, result_sel=IR_CONST4, // 4) BR_IF_NOT_ZERO (bnz rj, ir_const4) if c_out then goto branch else goto fetch0 endif; opcode[5]: a_sel=0, b_sel=0, alu_sel=AND, r6_write, result_sel=IR_CONST8, goto branch; // 5) JUMP (jump ir_const8) opcode[6]: ri_sel, rj_sel, alu_sel=ADDA, goto fetch0; // 6) MOVE (ri <- rj) opcode[7]: rj_sel, alu_sel=ADDA, mar_sel=LOAD, goto opcode7.1; // 7) STORE_BYTE (mem[rj] <= rk) opcode[8]: rj_sel, alu_sel=ADDA, mar_sel=LOAD, goto opcode8.1; // 8) LOAD_BYTE (ri <- mem[rj]) opcode[9]: rj_sel, r6_write, alu_sel=ADDA, goto opcode9.1; // 9) ? opcode[10]: ri_sel, rj_sel, rk_sel, c_in, alu_sel=SUB, goto fetch0; // 10) SUB (ri <- rj - rk) opcode[11]: goto opcode[11]; // 11) HALT opcode[12]: rj_sel, alu_sel=SUBA, r6_write, result_sel=IR_CONST4, if c_out then goto label_4 else goto branch endif; branch: r7_write, a_sel=7, b_sel=6, alu_sel=ADD, goto fetch0; opcode7.1: a_sel=5, b_sel=5, alu_sel=SUB, c_in, r5_write; rk_sel, a_sel=5, alu_sel=OR, mdr_sel=LOAD_ALU; memwrite: write, if wait then goto memwrite else goto fetch0 endif; opcode8.1: read, mdr_sel=LOAD_MEM, if wait then goto opcode8.1 endif; result_sel=MDR, ri_sel, goto fetch0; opcode9.1: r5_write, r4_write, a_sel=4, b_sel=4, alu_sel=SUB, c_in; r4_write, a_sel=4, b_sel = 4, alu_sel=ADD, c_in; r4_write, a_sel=4, b_sel = 4, alu_sel=ADD, c_in; r4_write, a_sel=4, b_sel = 4, alu_sel=ADD, c_in; loop: r4_write, a_sel=4, alu_sel=SUBA, if c_out then goto label_1 endif; ri_sel, a_sel=5, alu_sel=ADDA, goto fetch0; label_1: r6_write, a_sel=6, b_sel=6, alu_sel=ADD, if c_out then goto label_2 else goto label_3 endif; label_2: r5_write, a_sel=5, b_sel=5, alu_sel=ADD, c_in, goto loop; label_3: r5_write, a_sel=5, b_sel=5, alu_sel=ADD, goto loop; label_4: rj_sel, alu_sel=ADDA, r6_write, result_sel=IR_CONST4, if m_7 then goto branch else goto fetch0 endif; Microcode file used in Mythsim, for use with questions on this test. The microcode is very similar to that discussed in class. Differences are the addition of opcodes 4 (bnz) and "mystery" opcodes 9 & 12. For convenience you may want to tear off this sheet from the rest of the test. You do not need to turn in this sheet.