Midterm Exam 3 - Computer Architecture II | CS 232, Exams of Computer Architecture and Organization

Download Midterm Exam 3 - Computer Architecture II | CS 232 and more Exams Computer Architecture and Organization in PDF only on Docsity! 1 CS232 Midterm Exam 3 April 27, 2005 100Total +63 502 501 Your ScoreMaximumQuestion Name: Section:  This exam has 6 pages (nothing to tear off this time).  You have 50 minutes, so budget your time carefully!  No written references or calculators are allowed.  To make sure you receive credit, please write clearly and show your work.  We will not answer questions regarding course material. 2 Question 1: Pipelined Datapath (50 points) Here is the final datapath that we discussed in class, much like the one we built in Verilog. Branches are resolved in the decode stage. Part (a) If branches are not predicted, how many stall/flush cycles would be required for each branch? Assume no data hazards. (5 points) As drawn, there is an unsupported data hazard when branches use register values computed by earlier instructions, e.g., add $3, $1, $2 bne $3, $0, branch target Part (b) Add forwarding data paths to correctly support all data hazards for the bne instruction to the data path below. Hint: by forwarding from the ALU output (marked with a dot), you can avoid adding new stalls. (15 points) Zero Result 0 1 0 1 0 1 0 1 2 0 1 0 1 2 0 1 4 0 Adrs Data RAM Data Forward Control Hazard + + P C Adrs Instr. RAM R1 R2 Wr Data 1 2 Regs = ID/EX.RegisterRt ID/EX.MemRead Rt Rs P C W rit e IF /I D .W ri te × 4 Ext IF.Flush Rt Rd Rs IF /ID ID /E X E X /M E M M E M /W B EX/Mem.RegRd MEM/WB.RegisterRd MEM/WB.RegWrite E X /M em .R eg W rit e ControlMux 5 Question 2, continued Part (e) Given a direct-mapped cache with 4 blocks of 8 bytes, which of the following byte accesses hit? For those accesses that hit indicate whether the hit is because of spatial locality, temporal locality, or neither in the reason column. (20 points) Part (f) If you were given a processor’s base CPI (i.e., the CPI that a processor would have if it never missed in the data cache), what information would you need in order to compute its CPI with a real cache? (5 points) 011100 --- Reason 111111 000111 110111 111111 000100 011111 010000 111111 010101 Miss000000 Hit/MissAddress (binary) Address Tag Index Block offset 6 Problem 3, More Pipelined Datapath (+6 extra credit points) Below is a MIPS pipelined datapath, annotated with some signal values. Select the instructions in each pipe stage that are consistent with the annotated signal values. Be careful, these are tricky because we’ve included some values that are correct, but will be ignored (e.g., the memory address is ignored by the instruction in the MEM stage). A good approach to this problem is to eliminate the answers that are inconsistent with the data path. (+2 points each) Zero Result 0 1 0 1 0 1 0 1 2 0 1 0 1 2 0 1 4 0 Adrs Data RAM Data Forward Control Hazard + + P C Adrs Instr. RAM R1 R2 Wr Data 1 2 Registers = ID/EX.RegisterRt ID/EX.MemRead Rt Rs P C W rit e IF /I D .W ri te × 4 Ext IF.Flush Rt Rd Rs IF /ID ID /E X E X /M E M M E M /W B $s1 MEM/WB.RegisterRd MEM/WB.RegWrite E X /M em .R eg W rit e ControlMux ID stage a) add $t0, $s0, $v0 b) bne $t0, $s0, label c) bne $s0, $v0, label d) add $s0, $v0, $t0 e) bne $v0, $t0, label $t0 $s0 $v0 0 reg write 0 1 $ra mem write 0 EX stage a) sub $t0, $s8, $t0 b) addi $t0, $s0, 100 c) subi $s1, $t0, 100 d) addi $a2, $s1, 100 e) sub $t0, $t0, $s1 WB stage a) sw $t0, -4($v0) b) addi, $ra, $v0, 100 c) lw $a1, 16($s1) d) sll $ra, $s1, $t0 e) sub $s1, $ra, $a3 $t0 1 0x F 02 0 100 IF stage MEM stage R-type: op rd, rs, rt I-type: op rs, rt, imm op rt, imm(rs)