Download CPE 426 Midterm: VHDL Programming at UAH ECE Department and more Exams Engineering in PDF only on Docsity! The University of Alabama in Huntsville ECE Department CPE 426 01 Midterm Exam October 16, 2007 Name: _______________________________ 1. (15 points) (a) ( 4 points) Create a VHDL entity named mux_16_to_1 that represents a 16 to 1 multiplexor. (b) (11 points) Create a VHDL architecture representing a structural model of the 16 to1 mux using as many mux_4_to_1 muxes as are needed. You do not need to write an entity or an architecture for mux_4_to_1. You may also assume that a component has already been declared and that no configuration statement is required. 2. (1 point) The synthesizable subset of VHDL is standard. (True/False) _____ 3. (20 points).(a) (12 points) Write a VHDL function that will take two integer vectors, A and B, and find the dot product C = ฮฃ ai * bi. The function call should be of the form DOT(A,B), where A and B are integer vector signals. Use attributes inside the function to determine the length and range of the vectors. Make no assumptions about the high and low values of the ranges. For example, A(3 downto 1) = (1,2,3), B(3 downto 1) = (4,5,6), C = 3*6 + 2*5 + 1*4 = 32. A(0 to 4) = (1,3,5,7,9), B(9 downto 5) = (2,4,6,8,10) = 1*2 + 3*4 + 5*6 + 7*8 + 9*10 = 190 Output a warning if the ranges are not the same. (b)(8 points) Show an architecture that includes two calls to the function with the following properties. 1 - returns a value, 2 โ triggers a warning message. 13. (15 points) Design a priority encoder that is described by the following truth table. (d is for donโt care)(a)(3 points) Write a VHDL entity. (b) (6 points) Use concurrent signal assignments to implement the architecture. (c) (6 points) Use sequential statements to implement the architecture. Include any necessary library references. Inputs Outputs D0 D1 D2 D3 x y v 0 0 0 0 Z Z 0 1 0 0 0 0 0 1 d 1 0 0 0 1 1 d d 1 0 1 0 1 d d d 1 1 1 1 14. (10 points) Draw the state diagram for the following state machine. Is it a Moore machine or a Mealy machine? ENTITY state_machine IS PORT (sig_in ; IN BIT; clk, rst : IN BIT; sig_out : OUT BIT); END state_machine; ARCHITECTURE state_machine OF state_machine IS TYPE state_type IS (a, b, c, d, e); SIGNAL current_state, next_state : state_type; BEGIN PROCESS (sig_in, current_state) BEGIN sig_out <= โ0โ; next_state <= c; CASE current_state WHEN a => IF sig_in = โ0โ THEN next_state <= a; sig_out <= โ1โ; ELSE next_state <= d; sig_out <= โ1โ; END IF; WHEN b => IF sig_in = โ0โ THEN next_state <= b; ELSE next_state <= c; END IF; sig_out <= โ1โ; WHEN c => IF sig_in = โ1โ THEN sig_out <= โ1โ; next_state <= a; ELSE next_state <= b; END IF; sig_out <= โ1โ; WHEN d => IF sig_in = โ0โ THEN next_state <= e; END IF; WHEN e => IF sig_in = โ1โ THEN next_state <= c; END IF; END CASE; END PROCESS; PROCESS (clk) BEGIN IF (rst = โ0โ) then current_state <= a; ELSIF (clkโEVENT AND clk = โ1โ) THEN current_state <= next_state; END IF; END PROCESS; END state_machine;
