Download Computer Architecture Exam - Spring 2006 and more Exams Computer Architecture and Organization in PDF only on Docsity! Comprehensive Exams COMPUTER ARCHITECTURE Spring 2006 April 3, 2006 ID Number ____________________________ 1 /15 2 /20 3 /20 4 /20 Total /75 Problem 1. ( 15 points) Logic Design: A three-input switching function is expressed as f(a, b, c) = (a + bc)(a ′b + c). a) Write function f(a, b, c) in the minimum sum of products format. b) Write function f(a, b, c) in the minimum product of sums format. c) Suppose we connect the output of the function f to the input of one D Flip-Flop, and connect the output of the D Flip-Flop, g, to signal a, we have a sequential machine with inputs (b, c) and output g. Write the state table of the sequential machine. II) This question asks about the prospect of adding the SETC instruction to a multicycle processor. Here is some extra information: • Cycle time is 50ns • Assume that a STORE instruction takes 3 cycles STORE Cycle 1: Fetch and Decode STORE Cycle 2: Compute address and read register STORE Cycle 3: Write to memory • BNE and ADDI take 2 cycles each • Assume that the SETC instruction takes o 1 cycle to be fetched and decoded o 1 cycle to get ready to store the first word o 1 cycle to store each word (this includes time to keep track of how many words were written, and to increment the address to store to). A) How long would it take to accomplish the setc functionality in the original design (without the SETC instruction)? Give an answer in cycles. B) Consider a multicycle implementation of the SETC instruction. How many cycles would it require? C) If you were asked to advise a company considering a multicycle design including the SETC instruction, would you recommend that they go forward with the project? Answer yes or no and provide a few sentences of English explanation. III) This question asks about the prospect of adding the SETC instruction to a pipelined processor. Here is some extra information: • Assume that the cycle time is 50ns • Assume the pipeline has these 5 stages (just like the DLX pipeline developed in Patterson and Hennessey): fetch, decode, execute, memory, writeback A) Some further assumptions for Part A • Assume that you cannot change the number of pipeline stages • Assume that you cannot change the design of the memory module (it can store only one value per cycle) Is it possible to implement the SETC instruction in a pipelined design? Answer yes or no and give a few English sentences of explanation. B) If the assumptions from Part A are removed (that is you can modify the pipeline design), would you recommend doing so? Answer yes or no and provide a few sentences of English explanation. if id memex2ex1reg wb 3. (20 points) Pipelining A certain processor has a pipeline as shown above. Registers are read in stage reg and written in wb. There are two execution stages, ex1 and ex2. Arithmetic operations (add, sub, etc.) complete the computation at the end of ex2, but logical operations (e.g., and, or, shift) produce the result by the end of ex1. Memory (cache) is accessed in stage mem, while the address calculation for memory operations is done in ex1 and ex2. Assume all reasonable forwarding (if you need to make other assumptions, make sure they are reasonable ones, and clearly stated). Show all forwarding and bubbles for the following code on this pipeline. add $5, $4, $1 IF ID R X1 X2 M WB lw $6, 1000($5) and $6, $6, $4 add $8, $5, $6 lw $7, 1020($5) and $9, $8, 46 add $10, $7, $9 B) Could this code be reordered to improve performance? If so, how many fewer stalls would result?
