Download Minitab Laboratory 2 - Regression Analysis | CPSC 5155G and more Study notes Computer Architecture and Organization in PDF only on Docsity! Sequencing the Major State Register Recall that the hardwired control unit is based on two interrelated registers: the Minor State Register and the Major State Register. The Minor State Register is a modulo–4 counter, producing the sequence T0, T1, T2, and T3 continuously while the computer is running. T3 from the Minor State Register is the trigger for the Major State Register to change. This causes the Major State Register to accept control input and possibly change on the rising edge of the T0 pulse. The possible sequences of the Major State Register follow three patterns 1. Fetch to Fetch 2. Fetch to Execute 3. Fetch to Defer to Execute The sequencing of the Major State Register depends on two control signals generated by the control unit. These are called S1 and S2. The State Diagram for the Major State Register Here is the state diagram for the register. It has three states: F, D, and E. The two control signals S1 and S2 control the sequence of this register. If the present state is Fetch (F) then If S1 = 0, the next major state will be Fetch. If S1 = 1 and S2 = 0, the next major state will be Execute. If S1 = 1 and S2 = 1, the next major state will be Defer. If the present state is Defer (D), the next state will be Execute. If the present state is Execute (E), the next state will be Fetch. Generation of the S2 Control Signal Generation of the S2 control signal is simplified by the fact that it is used only in combination with the S1 control signal. Technically we should say that S2 = IRIR 3031 IR29 IR26. However the first part is handled by the S1 control signal, so S2 = IR29 IR26. Again, here is the state diagram for the Major State Register. Design of the Major State Register The Major State Register is implemented by two D flip–flops, D1 and D0. The inputs to these flip–flops are derived from the major state and the signals S1 and S2. The trigger for the state transitions is the T3 pulse from the Minor State Register. The binary encoding for the major states is shown in the following table. State Y1 Y0 F 0 0 D 0 1 E 1 0 We note that the circuit, when operating properly, never has both D1 = 1 and D0 = 1. Thus we may say that D1 = conditions to move to Execute D0 = conditions to move to Defer This gives rise to the following equations. D0 = FS1S2 // F = 1 if and only if the major state is Fetch D1 = SSF 21 + D // D = 1 if and only if the major state is Defer Circuitry for the Major State Register
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