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MIPS Code, Average Memory Access Time-Computer Architecture and Assembly Language-Assignment, Exercises of Computer Architecture and Organization

I am student at Baddi University of Emerging Sciences and Technologies. To help my friends in other universities, I am uploading my assignments of different courses. Its for Computer Architecture and Assembly Language course. Other can see if they are searching following: Speculative, Processor, Buffer, Mip, Code, Reservation, Station, Cycle, Cache, Memory, Bus

Typology: Exercises

2011/2012

Uploaded on 08/01/2012

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Download MIPS Code, Average Memory Access Time-Computer Architecture and Assembly Language-Assignment and more Exercises Computer Architecture and Organization in PDF only on Docsity! CS704 – Advanced Computer Architecture­II      Due Date: 17th July, 2012        Assignment 3          Instructions to Solve Assignments    The purpose of  assignments  is  to  give you hands on practice.  It  is  expected  that  students  will solve the assignments themselves. Following rules will apply during the evaluation of  assignment.    • Cheating from any source will result in zero marks in the assignment.  • Any student  found cheating  in any  two of  the assignments submitted will be awarded  "F" grade in the course.  • No assignment after due date will be accepted.  docsity.com Question 1: Total Points (10+10=20)  Consider  the  speculative  processor  discussed  in  lectures.  Since  the  reorder  buffer  contains a value field, you might think that the value field of the reservation stations  could be eliminated.   (a) Show an example where this is the case and an example where the value field of  the reservation stations  is still needed. Use the speculative processor shown in  Figure  1.1.  Show  MIPS  code  for  both  examples.  How  many  value  fields  are  needed in each reservation station?  (b) Find a modification to the rules for instruction commit that allows elimination of  the value fields  in the reservation station. What are the negative side effects of  such a change?    FIGURE 1.1 The basic structure of a MIPS FP unit using Tomasulo’s algorithm and extended  to handle speculation.      Question 2: Total Points (5+5+5+5=20)  For this problem, assume that you have a processor with a cache connected to main  memory  via  a  bus.  A  cache  access  takes  1  cycle.  A  successful  cache  access  (a  hit)  finishes within that cycle. On an unsuccessful access (a miss) additional work must  docsity.com
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