Download MIPS Datapath for Assignment 4 - Computer Architecture - Fall 2007 | ECE 3055 and more Assignments Electrical and Electronics Engineering in PDF only on Docsity! Summer 2007 ECE 3055 Assignment 4 Due Date: 11:59 pm, Monday July 9th, 2007. 1 Purpose: To understand the operation of the pipelined MIPS datapath, particularly the timing requirements for correctly dealing with forwarding and control and data hazards. 1.1 Assignment As with Part I there are two components – a warm-up component designed to help you become familiar with the datapath and an extension component. 1.1.1 Warm-up 1. To familiarize yourself with the model, compile and execute a few simple programs. Study the trace and execution of the program that is provided. Study the trace and convince yourself that the programs are indeed correctly executed. Check the (brief) documentation associated with the model. The warm-up can be discussed with your classmates. a. Is this program execution correct? If not why not? b. The datapath does not provide hardware support for correctly executing branches? How many delay slots does the pipeline have? c. What is the initial value of the stack pointer? d. What value is placed on the read output of memory when the data memory is not being read? 1.1.2 Extensions There are three parts to this assignment. 1. Extend the data path to implement data forwarding for the supported instructions. Your implementation should correctly execute all programs that have dependencies between instructions supported by the datapath. Note that there will still be a single delay slot in instances where there is a load ALU hazard. 2. Move the computation of the branch address and branch condition to the decode stage to realize a single branch delay slot. Demonstrate the correct execution with 2 sample programs that fill branch and load delay slots with useful instructions. 3. Extend the datapath with a hazard detection unit that will perform the following operations in hardware a. Hazards between a load and an immediately following register-to-register operation will be detected and a single stall cycle (bubble) will be inserted into the pipeline. b. The fetch unit will implement assume-not-taken policy for branches. When a branch is actually taken, the incorrect instruction has to be flushed and the instruction fetch continued at the branch target.
