MOS Essentials - Lecture Slides | ECE 3040, Study notes of Electrical and Electronics Engineering

Download MOS Essentials - Lecture Slides | ECE 3040 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 Pierret Chapter 17 - MOS Essentials Jeff Davis ECE3040 Spring 2006 2 References • Prof. Alan Doolittle’s Notes – users.ece.gatech.edu/~alan/index_files/ECE3040index.htm • Prof. Farrokh Ayazi’s Notes – users.ece.gatech.edu/~ayazi/ece3040/ • Figures for Require Textbooks – (Pierret and Jaeger) 5 MS Junction in Equilibrium ! M > ! S 6 Forward and Reverse Bias Operation V A > 0 V A < 0 Lowers metal Fermi energy level Raises metal Fermi energy level 7 Ohmic Contact See notes from class! 10 Heavy Doped Junction produces Ohmic Contact Quantum Mechanical Tunneling allows current to flow both ways with low resistance! HIGH DOPING! 11 Flow of current from “Source” to “Drain” is controlled by the “Gate” voltage. Control by the Gate voltage is achieved by modulating the conductivity of the semiconductor region just below the gate. This region is known as the channel MOS Transistor Qualitative Description 12 G S D B VGS VBS VDS + + + - n-channel MOS Transistor G=Gate, D=Drain, S=Source, B=Body (substrate, but to avoid confusion with substrate, B is used) G S D B VSG VSB VSD - - - + p-channel MOS Transistor Note: All voltages are shown in their “positive “ direction. Obviously, VYX=-VXY for any voltage MOS Transistor Qualitative Description 15 VDS = 0 VGS > VT An induced n- type region, an “inversion layer”, forms in the channel and “electrically connects” the source and drain. P-type Inversion layer (n-type) N-channel MOS Transistor Qualitative Description 16 VGS > VT(continued): The induced n- type region allows current to flow between the source and drain. The induced channel acts like a simple resistor. Thus, this current, ID, depends linearly on the Drain voltage VD. This mode of operation is called the linear or “triode”* region. P-type Inversion layer (n-type) Small positive VDS N-channel MOS Transistor Qualitative Description 17 Inversion case, VGS > VT(continued): Drain current verses drain voltage when in the linear or “triode”* region. N-channel MOS Transistor Qualitative Description Linear region 20 Inversion case, VGS > VT(continued): •The inversion layer eventually vanishes near the drain end of the channel. •This occurs at VGS - VT because the gate to channel potential at the drain side is at the threshold voltage. •This is called “Pinch-Off” and results in a Flat ID-VDS curve N-channel MOS Transistor Qualitative Description 21 Inversion case, VGS > VT(continued): ID-VDS curve for the “Saturation Region” The drain-source voltage, VDS, at which this occurs is called the saturation voltage, Vsat while the current is called the saturation current, IDsat. IDsat N-channel MOS Transistor Qualitative Description Saturation region Linear Region VDsat = saturation voltage = VGS-VT 22 Inversion case, VGS > VT(continued): For VDS>Vsat the channel length, L, effectively changes by a value ΔL. The region of the channel, ΔL is depleted and thus, is high resistivity. Accordingly, almost all voltage increases in VDS>Vsat are “dropped across” this portion of the channel. N-channel MOS Transistor Qualitative Description 25 MOS Transistor I-V Derivation With our expression relating the Gate voltage to the surface potential and the fact that φS=2φF we can determine the value of the threshold voltage ( ) ( ) areaunit per ecapacitanc oxide theis where, devices) channel-p(for 2 2 2 devices) channel-n(for 2 2 2 ox ox ox F S D ox S FT F S A ox S FT x C qN C V qN C V ! " ! ! " " ! ! " = ##= += Where we have made use of the use of the expression, oSS K !! = 26 Quantitative Description of MOSFET Current 27 ZEROTH ORDER CAPACITOR CURRENT MODEL FIRST ORDER SQUARE LAW CURRENT MODEL SECOND ORDER BULK CHARGE CURRENT MODEL Different Current Models for Enhanced Understanding! 30 ZEROTH ORDER CAPACITOR CURRENT MODEL 31 Zeroth Order Capacitor Current Model n+ n+!x !y VDS > 0 drainsource E I = Charge Passing Through Surface S Given time interval Surface S Z Z = width of the transistor device 32 Zeroth Order Capacitor Current Model n+ n+!x !y VDS > 0 drainsource E I = total charge in volume V time to move total charge OUT of V =- QI!yZ !t Surface S Z Volume V Q I = inversion charge per unit area 35 Zeroth Order Capacitor Current Model I= ! C ox (VGS !VT )µZE ur I=C ox (VGS !VT )µZ dV dy Idy = C ox (VGS !VT )µZdV IL = C ox (VGS !VT )µZ(VDS ) I ! C ox µ Z L (V GS "V T )V DS E = ! dV dy Integrate both sides! 36 Zeroth Order Capacitor Current Model IDS VDSVDS = VGS - VT I ! C ox µ Z L (V GS "V T )V DS I ! C ox µ Z L (V GS "V T ) 2 Linear region Saturation region 37 FIRST ORDER SQUARE LAW CURRENT MODEL 40 Drain Current-Voltage Relationship In the Linear Region, VGS>VT and 0<VDS<Vdsat ID = !ZµnQN d" dy ID y=0 y=L # dy = !Zµn QNd""= 0 " =VDS # IDL = !Zµn QNd""= 0 " =VDS # ID = !Zµn L QNd""= 0 " =VDS # We need an expression relating φ and QN First Order Square Law Model Derivation 41 “Capacitor-Like” Model for QN Neglect all but the mobile inversion charge MOS Capacitor MOS Transistor ( ) TGS VVfor !""# TGSoxN VVCQ ( ) TGS VVfor ! """# $TGSoxN VVCQ Source Drain , dV dQ CSince ox = Neglect the depletion region charge 42 ID = !Zµn L QNd""= 0 " =VDS # ID = !Zµn L !Cox VG !VT !"( )d""= 0 " =VDS # ID = ZµnCox L VGS !VT( )VDS ! VDS 2 2 $ % & ' ( ) 0 *VDS *VDsat and VGS +VT This is known as the “square law” describing the Current-Voltage characteristics in the “Linear” or “Triode” region. First Order Square Law Model Derivation 45 Deviations From Ideal Channel Length Modulation Effect Above “pinch-off” (when VDS>VDsat=VGS-VT) the channel length reduces by a value ΔL. Thus, the expression for drain current, Becomes, I D = I Dsat = Zµ n C ox 2L V GS !V T( ) 2" # $ % V Dsat &V DS I D = I Dsat = Zµ n C ox 2 L ! "L( ) V GS !V T( ) 2# $ % & VDsat 'VDS or since "L((L, 1 L ! "L ) 1 L 1+ "L L * +, - ./ I D = I Dsat = Zµ n C ox 2L V GS !V T( ) 2# $ % & 1+ "L L * +, - ./ V Dsat 'V DS 46 MOS Transistor: Deviations From Ideal Channel Length Modulation Effect DS V L L != " But the fraction of the channel that is pinched off depends linearly on VDS so, I D = I Dsat = Zµ n C ox 2L V GS !V T( ) 2" # $ % 1+ & V DS( ) VDsat 'VDS where λ is known as the Channel-Length Modulation parameter and is typically: 0.001 V-1 < λ <0.1 V−1 Channel Length Modulation causes the dependence of drain current on the drain voltage in saturation. 47 MOS Transistor: Deviations From Ideal Body Effect (Substrate Biasing) Until now, we have only considered the case where the substrate (Body) has been grounded…. …but the substrate (Body) is often intentionally biased such that the Source-Body and Drain-Body junctions are reversed biased. The body bias, VBS, is known as the backgate bias and can be used to modify the threshold voltage. Note that now our channel potential has an offset equal to VBS, …. 50 nMOS Transistor: Enhancement Mode verses Depletion Mode MOSFET We have been studying the “enhancement mode” MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). It is called “enhancement” because conduction occurs only after the channel conductance is “improved” or “enhanced”. In this case, VTN>0 Transistors can be fabricated such that: These transistors have conduction for VGS=0 due to a channel already existing without the need to “invert the near surface region”. To modulate currents, a field must applied to the gate that depletes the channel. Thus, transistors of this nature are called “Depletion mode MOSFETs”. V TN ! 0 MOS Transistor: Enhancement Mode verses Depletion Mode MOSFET n-channel MOSFET I Ss G D aah oF No channel when Vg = 0 All Vg>0 Vg=0, Vg<0 Enhancement mode Vp Depletion mode ‘ t wl E Lg Channel when Vg =0 ———— ——— Structure Symbol Characteristics MOSFET operational modes. V, = 0 channel status, circuit symbol, and /)-Vp characteristics of n-channel enhancement-mode and depletion-mode MOSFETs. 51 52 MOS Transistor: Summary Jaeger uses the notation: Pierret)in (Z Width Gate theis W where PMOS Pierret)in (Z Width Gate theis W where ' ' L W C L W KK L W C L W KK NMOS oxnpp oxnnn µ µ == == 4-Terminal 3-Terminal NMOS (n-channel) PMOS (p-channel) Enhancement EnhancementDepletion Depletion 55 For small signals…linear relationship VGS ID IDS = Kn 2 VGS !VTN( ) 2" # $ % 1+ & VDS( ) for VDS 'VGS !VTN VTVDS 56 MOSFET Small Signal Model and Analysis Linear Two Port Network + V1 - i1 i2 + V2 - I1=y11V1 + y12V2 I2=y21V1 + y22V2 General “y-parameter” Network Non-Linear I-V relationship (BJT, MOSFET, etc…) + V1 - i1 i2 + V2 - Linearize over “small signal range” igs=y11vgs + y12vds ids=y21vgs + y22vds MOSFET “y-parameter” Network vGS vDS iDS iGS 57 i1=y11v1 + y12v2 i2=y21v1 + y22v2 Equivalent circuit for two port network - admittance Matrix 60 vGS iD VT y 21 = ids vgs vds =0 = diDS dvgs vGS =VDS This is the slope of the linear relationship between ids and vgs; therefore we calculate the slope at the DC bias point in the large signal model! VGS Calculating two-port Network Parameters 61 Calculating two-port Network Parameters IDS = Kn 2 VGS !VTN( ) 2" # $ % 1+ & VDS( ) for VDS 'VGS !VTN MOSFET Amplifiers are biased into Saturation (or Active Mode) y 11 = igs vgs vds =0 = diGS dvGS vGS =VGS y 21 = ids vgs vds =0 = diDS dvGS vGS =VGS y 12 = igs vds vgs =0 = diGS dvDS vDS =VDS y 22 = ids vds vgs =0 = diDS dvDS vDS =VDS 62 igs=y11vgs + y12vds ids=y21vgs + y22vds igs vgs ids vds y 11 = igs vgs vds =0 = diGS dvGS vGS =VGS y 21 = ids vgs vds =0 = diDS dvGS vGS =VGS y 12 = igs vds vgs =0 = diGS dvDS vDS =VDS y 22 = ids vds vgs =0 = diDS dvDS vDS =VDS 0 0 y12vds y21vgs 65 Calculating two-port Network Parameters iDS = Kn 2 VGS !VTN( ) 2" # $ % 1+ & VDS( ) for VDS 'VGS !VTN MOSFET Amplifiers are biased into Saturation (or Active Mode) y 22 = ids vds vds =0 = diDS dvDS vDS =VDS ,vGS =VGS = d dvDS Kn 2 vGS !VTN( ) 2" # $ % 1+ & vDS( ) ' () * +, y 22 = Kn 2 & VGS !VTN( ) 2" # $ % ' () * +, 66 MOSFET Small Signal Model and Analysis Putting the mathematical model into a small signal equivalent circuit gm = Kn VGS !VTN( )"# $% 1+ & VDS( )( ) go = 1 Kn 2 ! VGS "VTN( ) 2# $ % & ' () * +, 67 MOSFET Small Signal Model and Analysis Putting the mathematical model into a small signal equivalent circuit Compare this to the BJT small signal equivalent circuit 70 MOSFET Small Signal Model and Analysis Example: Jaeger 13.94 ( ) ( ) [ ]VV v v v v v v A kmSRRdrg v v and Megk Meg v v v v v v v v A GS o s GS s o v om GS o s GS GS o s GS s o v /27.7 35.748.31.2399.0 110 1 !===" !=!=!== + = == 71 MOSFET Small Signal Model and Analysis Add in capacitances Reverse Bias Junction capacitances Overlap of Gate Oxide Gate to channel to Bulk capacitance Overlap of Gate Oxide LD LD 72 MOSFET Small Signal Model and Analysis Complete Model of a MOSFET Reverse Bias Junction capacitances Overlap of Gate Oxide and Gate to channel capacitance Overlap of Gate Oxide Gate to channel to Bulk capacitance FSB mmb V gg ! " 22 + = Due to effective modulation of the threshold voltage. 75 MOSFET Small Signal Model and Analysis SPICE MOSFET Model – Additional Parameters Most Used 76 MOSFET Amplifiers What is the Maximum Gain Possible? ( )( ) ( ) ( ) ( )TGS DS Maxv TGSn DSTGSn Maxv omMaxv VV V A VVK VVVK A vgA ! + != ! +! != != " " " " 1 1 , 2, , Saturated! Issatisfied. always0 , MOSFET modedepletion afor 0 ,current)?(Constant !"> # = "> isV soVand VVbut VVVsaturateditIs TP TP GSDS TPGSDS go is internal to the transistor and can not be avoided. Any additional resistor due to external circuitry will lower the gain. For this reason current sources are often used as the “load” instead of bias resistors in amplifier circuits. Gate Bias AC Signal 77 MOS Transistor: Bias Circuitry-Enhancement Mode NMOS Due to zero DC current flow in the gate, the bias analysis of a MOSFET is significantly easier than a BJT. A B C •Form Thevenin circuits looking out the gate, drain, and source 80 MOSFET Small Signal Model and Analysis •Just as we did with the BJT, we can consider the MOSFET amplifier analysis in two parts: •Find the DC operating point •Then determine the amplifier output parameters for very small input signals. 81 ( ) ( ) devices) channel-p(for 2 2 2 devices) channel-n (for2 2 2 F S D ox S FT F S A ox S FT qN C V qN C V ! " " ! ! " " ! ##= += MOS Transistor: Deviations From Ideal Body Effect (Substrate Biasing) Thus, our threshold potential with the body grounded, Becomes, ( ) ( ) devices) channel-p(for 2 2 2 devices) channel-n(for 2 2 2 BSF S D ox S BSFGB BSF S A ox S BSFGB V qN C VV V qN C VV Threshold Threshold +!!!= !+!= " # # " " # # " But we would like to have this in terms of VGS instead of VGB. Since, VGS =VGB+VBS ( ) ( ) devices) channel-p(for 2 2 2 devices) channel-n(for 2 2 2 BSF S D ox S FGS BSF S A ox S FGS V qN C V V qN C V Threshold Threshold +!!= !+= " # # " " # # " Surface Potential φS VT=