MOS Transistor Theory, Slides of Engineering Physics

Download MOS Transistor Theory and more Slides Engineering Physics in PDF only on Docsity! 1 EE 261 Krish Chakrabarty 1 MOS Transistor Theory • So far, we have viewed a MOS transistor as an ideal switch (digital operation) – Reality: less than ideal EE 261 Krish Chakrabarty 2 Introduction • So far, we have treated transistors as ideal switches • An ON transistor passes a finite amount of current – Depends on terminal voltages – Derive current-voltage (I-V) relationships • Transistor gate, source, drain all have capacitance – I = C (∆V/∆t) -> ∆t = (C/I) ∆V – Capacitance and current determine speed • Also explore what a “degraded level” really means 2 EE 261 Krish Chakrabarty 3 MOS Transistor Theory • Study conducting channel between source and drain • Modulated by voltage applied to the gate (voltage- controlled device) • nMOS transistor: majority carriers are electrons (greater mobility), p-substrate doped (positively doped) • pMOS transistor: majority carriers are holes (less mobility), n-substrate (negatively doped) EE 261 Krish Chakrabarty 4 Terminal Voltages • Mode of operation depends on Vg, Vd, Vs – Vgs = Vg – Vs – Vgd = Vg – Vd – Vds = Vd – Vs = Vgs - Vgd • Source and drain are symmetric diffusion terminals – By convention, source is terminal at lower voltage – Hence Vds ≥ 0 • nMOS body is grounded. First assume source is 0 too. • Three regions of operation – Cutoff – Linear – Saturation Vg Vs Vd VgdVgs Vds +- + - + - 5 EE 261 Krish Chakrabarty 9 nMOS Saturation • Channel pinches off • Ids independent of Vds • We say current saturates • Similar to current source + - Vgs > Vt n+ n+ + - Vgd < Vt Vds > Vgs-Vt p-type body b g s d Ids EE 261 Krish Chakrabarty 10 I-V Characteristics • In linear region, Ids depends on – How much charge is in the channel? – How fast is the charge moving? 6 EE 261 Krish Chakrabarty 11 Channel Charge • MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel • Qchannel = n+ n+ p-type body + Vgd gate + + source - Vgs - drain Vds channel- Vg Vs Vd Cg n+ n+ p-type body W L tox SiO2 gate oxide (good insulator, εox = 3.9) polysilicon gate EE 261 Krish Chakrabarty 12 Channel Charge • MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel • Qchannel = CV • C = n+ n+ p-type body + Vgd gate + + source - Vgs - drain Vds channel- Vg Vs Vd Cg n+ n+ p-type body W L tox SiO2 gate oxide (good insulator, εox = 3.9) polysilicon gate 7 EE 261 Krish Chakrabarty 13 Channel Charge • MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel • Qchannel = CV • C = Cg = εoxWL/tox = CoxWL • V = n+ n+ p-type body + Vgd gate + + source - Vgs - drain Vds channel- Vg Vs Vd Cg n+ n+ p-type body W L tox SiO2 gate oxide (good insulator, εox = 3.9) polysilicon gate Cox = εox / tox EE 261 Krish Chakrabarty 14 Channel Charge • MOS structure looks like parallel plate capacitor while operating in inversion – Gate – oxide – channel • Qchannel = CV • C = Cg = εoxWL/tox = CoxWL • V = Vgc – Vt = (Vgs – Vds/2) – Vt n+ n+ p-type body + Vgd gate + + source - Vgs - drain Vds channel- Vg Vs Vd Cg n+ n+ p-type body W L tox SiO2 gate oxide (good insulator, εox = 3.9) polysilicon gate Cox = εox / tox 10 EE 261 Krish Chakrabarty 19 nMOS Linear I-V • Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross dsI = EE 261 Krish Chakrabarty 20 nMOS Linear I-V • Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross channel ds QI t = = 11 EE 261 Krish Chakrabarty 21 nMOS Linear I-V • Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross channel ox 2 2 ds ds gs t ds ds gs t ds QI t W VC V V V L VV V V µ β =  = − −     = − −    ox = WC L β µ EE 261 Krish Chakrabarty 22 nMOS Saturation I-V • If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt • Now drain voltage no longer increases current dsI = 12 EE 261 Krish Chakrabarty 23 nMOS Saturation I-V • If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt • Now drain voltage no longer increases current 2 dsat ds gs t dsat VI V V Vβ  = − −    EE 261 Krish Chakrabarty 24 nMOS Saturation I-V • If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt • Now drain voltage no longer increases current ( )2 2 2 dsat ds gs t dsat gs t VI V V V V V β β  = − −    = − 15 EE 261 Krish Chakrabarty 29 pMOS I-V • All dopings and voltages are inverted for pMOS • Mobility µp is determined by holes – Typically 2-3x lower than that of electrons µn – 120 cm2/V*s in AMI 0.6 µm process • Thus pMOS must be wider to provide same current – In this class, assume µn / µp = 2 to 3 EE 261 Krish Chakrabarty 30 Capacitance • Any two conductors separated by an insulator have capacitance • Gate to channel capacitor is very important – Creates channel charge necessary for operation • Source and drain have capacitance to body – Across reverse-biased diodes – Called diffusion capacitance because it is associated with source/drain diffusion 16 EE 261 Krish Chakrabarty 31 Gate Capacitance • Approximate channel as connected to source • Cgs = εoxWL/tox = CoxWL = CpermicronW • Cpermicron is typically about 2 fF/µm n+ n+ p-type body W L tox SiO2 gate oxide (good insulator, εox = 3.9ε0) polysilicon gate EE 261 Krish Chakrabarty 32 The Gate Capacitance 17 EE 261 Krish Chakrabarty 33 Diffusion Capacitance • Csb, Cdb • Undesirable, called parasitic capacitance • Capacitance depends on area and perimeter – Use small diffusion nodes – Comparable to Cg for contacted diff – ½ Cg for uncontacted – Varies with process EE 261 Krish Chakrabarty 34 Diffusion Capacitance 20 EE 261 Krish Chakrabarty 39 Pass Transistor Ckts VDD VDD VSS VDD VDD VDD VDD VDD VDD EE 261 Krish Chakrabarty 40 Pass Transistor Ckts VDD VDD Vs = VDD-Vtn VSS Vs = |Vtp| VDD VDD-Vtn VDD-Vtn VDD-Vtn VDD VDD VDD VDD VDD VDD-Vtn VDD-2Vtn 21 EE 261 Krish Chakrabarty 41 Effective Resistance • Shockley models have limited value – Not accurate enough for modern transistors – Too complicated for much hand analysis • Simplification: treat transistor as resistor – Replace Ids(Vds, Vgs) with effective resistance R • Ids = Vds/R – R averaged across switching of digital gate • Too inaccurate to predict current at any given time – But good enough to predict RC delay EE 261 Krish Chakrabarty 42 RC Delay Model • Use equivalent circuits for MOS transistors – Ideal switch + capacitance and ON resistance – Unit nMOS has resistance R, capacitance C – Unit pMOS has resistance 2R, capacitance C • Capacitance proportional to width • Resistance inversely proportional to width kg s d g s d kC kC kC R/k kg s d g s d kC kC kC 2R/k 22 EE 261 Krish Chakrabarty 43 RC Values • Capacitance – C = Cg = Cs = Cd = 2 fF/µm of gate width – Values similar across many processes • Resistance – R ≈ 6 KΩ in 0.6um process – Improves with shorter channel lengths • Unit transistors – May refer to minimum contacted device (4/2 λ) – Or maybe 1 µm wide device – Doesn’t matter as long as you are consistent EE 261 Krish Chakrabarty 44 Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change 25 EE 261 Krish Chakrabarty 49 nMOS Operation Vgsn > Vtn Vdsn > Vgsn – Vtn Vgsn > Vtn Vdsn < Vgsn – Vtn Vgsn < Vtn SaturatedLinearCutoff Idsn Idsp Vout VDD Vin Vgsn = Vin Vdsn = Vout EE 261 Krish Chakrabarty 50 nMOS Operation Vgsn > Vtn Vin > Vtn Vdsn > Vgsn – Vtn Vout > Vin - Vtn Vgsn > Vtn Vin > Vtn Vdsn < Vgsn – Vtn Vout < Vin - Vtn Vgsn < Vtn Vin < Vtn SaturatedLinearCutoff Idsn Idsp Vout VDD Vin Vgsn = Vin Vdsn = Vout 26 EE 261 Krish Chakrabarty 51 pMOS Operation Vgsp < Vdsp < Vgsp < Vdsp > Vgsp > SaturatedLinearCutoff Idsn Idsp Vout VDD Vin EE 261 Krish Chakrabarty 52 pMOS Operation Vgsp < Vtp Vdsp < Vgsp – Vtp Vgsp < Vtp Vdsp > Vgsp – Vtp Vgsp > Vtp SaturatedLinearCutoff Idsn Idsp Vout VDD Vin 27 EE 261 Krish Chakrabarty 53 pMOS Operation Vgsp < Vtp Vdsp < Vgsp – Vtp Vgsp < Vtp Vdsp > Vgsp – Vtp Vgsp > Vtp SaturatedLinearCutoff Idsn Idsp Vout VDD Vin Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0 EE 261 Krish Chakrabarty 54 pMOS Operation Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp – Vtp Vout < Vin - Vtp Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp – Vtp Vout > Vin - Vtp Vgsp > Vtp Vin > VDD + Vtp SaturatedLinearCutoff Idsn Idsp Vout VDD Vin Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0 30 EE 261 Krish Chakrabarty 59 Beta Ratio • If βp / βn ≠ 1, switching point will move from VDD/2 • Called skewed gate • Other gates: collapse into equivalent inverter Vout 0 Vin VDD VDD 0.5 1 2 10p n β β = 0.1p n β β = EE 261 Krish Chakrabarty 60 Noise Margins • How much noise can a gate input see before it does not recognize the input? Indeterminate Region NML NMH Input CharacteristicsOutput Characteristics VOH VDD VOL GND VIH VIL Logical High Input Range Logical Low Input Range Logical High Output Range Logical Low Output Range 31 EE 261 Krish Chakrabarty 61 Logic Levels • To maximize noise margins, select logic levels at VDD Vin Vout VDD βp/βn > 1 Vin Vout 0 EE 261 Krish Chakrabarty 62 Logic Levels • To maximize noise margins, select logic levels at – unity gain point of DC transfer characteristic VDD Vin Vout VOH VDD VOL VIL VIHVtn Unity Gain Points Slope = -1 VDD- |Vtp| βp/βn > 1 Vin Vout 0