MOS Transistors - CMOS Design Methodologies - Lecture Slides, Slides of Computer Science

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MOS Transistors • Silicon substrate doped with impurities • Adding or cutting away insulating glass (SiO2) • Adding wires made of polycrystalline silicon (polysilicon, poly) or metal, insulated from the substrate by SiO2 Drain Source Gate nn Drain Source Gate SiO2 (insulator) p-type (doped) substrate Drain Source Gate nMOS transistor pMOS transistor channel Width W Length L Conductor (poly) Docsity.com Silicon Lattice • Transistors are built on a silicon substrate • Silicon is a Group IV material • Forms crystal lattice with bonds to four neighbors Si SiSi Si SiSi Si SiSi Docsity.com nMOS Transistor • Four terminals: gate, source, drain, body • Gate – oxide – body stack looks like a capacitor – Gate and body are conductors – SiO2 (oxide) is a very good insulator – Called metal – oxide – semiconductor (MOS) capacitor – Even though gate is no longer made of metal n+ p GateSource Drain bulk Si SiO2 Polysilicon n+ Docsity.com nMOS Operation • Body is commonly tied to ground (0 V) • When the gate is at a low voltage: – P-type body is at low voltage – Source-body and drain-body diodes are OFF – No current flows, transistor is OFF n+ p GateSource Drain bulk Si SiO2 Polysilicon n+ D 0 S Docsity.com nMOS Operation Cont. • When the gate is at a high voltage: – Positive charge on gate of MOS capacitor – Negative charge attracted to body – Inverts a channel under gate to n-type – Now current can flow through n-type silicon from source through channel to drain, transistor is ON n+ p GateSource Drain bulk Si SiO2 Polysilicon n+ D 1 S Docsity.com Transistors as Switches • We can view MOS transistors as electrically controlled switches • Voltage at gate controls path from source to drain g s d g = 0 s d g = 1 s d g s d s d s d nMOS pMOS OFF ON ON OFF Docsity.com MOS Transistor Switches N a b s N-switch a b s S = 0 S = 1 Good 0, Poor 1 0 1 0 1(degraded) Docsity.com MOS Transistor Switches P-switch a b s P a b s S = 1 S = 0 Good 1, Poor 0 1 0 1 0(degraded) a b s s CMOS switch a b s C S = 0 S = 1 a Good 0 Good 1 (Transmission gate) b s s Docsity.com CMOS Logic Gates-1 Inverter Input Outputa a VDD Gnd Pull-down Pull-up path path 2-input NAND Gnd VDD a b a b Pull-down Pull-up tree tree a b z z 0 0 Z 0 1 Z 1 0 Z 1 1 0 a b z 0 0 1 0 1 1 1 0 1 1 1 Z Pull-down Pull-up truth tabletruth table a b z 0 0 1 0 1 1 1 0 1 1 1 0 NAND truth table Docsity.com CMOS Inverter 01 0 YA VDD A=1 Y=0 GND ON OFF A Y Docsity.com CMOS Inverter 01 10 YA VDD A=0 Y=1 GND OFF ON A Y Docsity.com CMOS NAND Gate 1 1 0 0 A 11 0 1 10 YB A=0 B=1 Y=1 OFF OFF ON ON Docsity.com CMOS NAND Gate 1 1 0 0 A 11 10 1 10 YB A=1 B=0 Y=1 ON ON OFF OFF Docsity.com CMOS NAND Gate 1 1 0 0 A 11 10 01 10 YB A=1 B=1 Y=0 ON OFF OFF ON Docsity.com 3-input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high if ANY input is 0 Docsity.com 3-input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high if ANY input is 0 A B Y C Docsity.com CMOS Compound (Complex) Gates-1 • What function is implemented by this circuit? z c d Gnd a b VDD a b c d Docsity.com Or-And-Invert (OAI) Gate a b c d e f g h F a b c Pull-up network d e f g h Gnd F • Generally, complex CMOS gates can be derived directly from maxterms of the function (as in a Karnaugh map) Docsity.com Transmission Gates • Pass transistors produce degraded outputs • Transmission gates pass both 0 and 1 well Docsity.com Transmission Gates • Pass transistors produce degraded outputs • Transmission gates pass both 0 and 1 well g = 0, gb = 1 a b g = 1, gb = 0 a b 0 strong 0 Input Output 1 strong 1 g gb a b a b g gb a b g gb a b g gb g = 1, gb = 0 g = 1, gb = 0 Docsity.com Nonrestoring Tristate • Transmission gate acts as tristate buffer – Only two transistors – But nonrestoring • Noise on A is passed on to Y A Y EN EN Docsity.com Tristate Inverter • Tristate inverter produces restored output – Violates conduction complement rule – Because we want a Z output A Y EN EN Docsity.com Tristate Inverter • Tristate inverter produces restored output – Violates conduction complement rule – Because we want a Z output A Y EN A Y EN = 0 Y = 'Z' Y EN = 1 Y = A A EN Docsity.com Gate-Level Mux Design • How many transistors are needed? 1 0 (too many transistors)Y SD SD= + Docsity.com Gate-Level Mux Design • How many transistors are needed? 20 1 0 (too many transistors)Y SD SD= + 4 4 D1 D0 S Y 4 2 2 2 Y 2 D1 D0 S Docsity.com Transmission Gate Mux • Nonrestoring mux uses two transmission gates Docsity.com 4:1 Multiplexer • 4:1 mux chooses one of 4 inputs using two selects Docsity.com 4:1 Multiplexer • 4:1 mux chooses one of 4 inputs using two selects – Two levels of 2:1 muxes – Or four tristates S0 D0 D1 0 1 0 1 0 1 Y S1 D2 D3 D0 D1 D2 D3 Y S1S0 S1S0 S1S0 S1S0 Docsity.com CMOS Exclusive-Nor Gate a b F = a b • 8-transistor implementation TG1 TG2 a b TG1 TG2 F 0 0 nonconducting conducting B (1) 0 1 nonconducting conducting B (0) 1 0 conducting nonconducting B (0) 1 1 conducting nonconducting B (1) • Better, 6-transistor implementation is possible! Docsity.com D Latch Operation CLK = 1 D Q Q CLK = 0 D Q Q D CLK Q Docsity.com D Flip-flop • When CLK rises, D is copied to Q • At all other times, Q holds its value • a.k.a. positive edge-triggered flip-flop, master- slave flip-flop Fl op CLK D Q D CLK Q Docsity.com D Flip-flop Design • Built from master and slave D latches QM CLK CLKCLK CLK Q CLK CLK CLK CLK D La tc h La tc h D Q QM CLK CLK Docsity.com Nonoverlapping Clocks • Nonoverlapping clocks can prevent races – As long as nonoverlap exceeds clock skew • We will use them in this class for safe design – Industry manages skew more carefully instead φ1 φ1φ1 φ1 φ2 φ2φ2 φ2 φ2 φ1 QM QD Docsity.com Design Representation Levels • Design domains – Behavioral – Structural – Physical Gajski and Kuhn’s Y-chart (layered like an onion) Behavioral Structural Physical (geometric) Chip Cells Polygons Transistors Gates Processor Boolean equations Differential equations Algorithms • Hardware description languages commonly used at behavioral level, e.g. VHDL, Verilog • Example: Consider the carry function co = ab + bc + cia Docsity.com Verilog Example (Behavioral) module carry (co, a, b, ci); output co; input a, b, ci; assign co = (a & b) | (a & ci) | (b & ci); end module Boolean equation form: Boolean truth table form: primitive carry (co, a, b, ci); output co; input a, b, ci; table // a b c co 1 1 ? : 1; 1 ? 1 : 1; ? 1 1 : 1; 0 0 ? : 0; 0 ? 0 : 0; ? 0 0 : 0; end table end module Timing information: module carry (co, a, b, ci); output co; input a, b, ci; Wire #10 co = (a & b) | (a & ci) | (b & ci); end module co changes 10 time units after a, b, or c changes Docsity.com