MOSFET Circuits – Electronic Device and Applications – Lab 4 | ECEN 3314, Lab Reports of Electrical and Electronics Engineering

Download MOSFET Circuits – Electronic Device and Applications – Lab 4 | ECEN 3314 and more Lab Reports Electrical and Electronics Engineering in PDF only on Docsity! ECEN 3314 Electronic Device and Applications Fall 2007 Lab. 4 MOSFET Circuits 1. Objective To investigate the simple digital and analog applications of MOSFET. 2. Components Required Resistors, capacitors, ALD1101/ALD1102 dual n-channel/p-channel matched MOSFET pair (it is not in the lab kit, one can purchase it from the electronic shop on the first floor). CD4007 is optional. 3. Equipment Required  DC power supply  Oscilloscope  Function generator  Digital multimeter. 4. Topics 1) I-V curve of MOSFETs. 2) Transmission gates 3) Inverters 4) NMOS amplifier. 5) (Milestone) Frequency response of NMOS amplifier with capacitive load. 5. Pre-lab MOSFET is the dominant type of transistors in integrated circuits; it has more than 90% of the market share of transistors. However, for discrete transistor parts, they are basically limited in the area of power electronics applications. Therefore, PSpcice does not have so many small signal MOSFET models as in the case of BJT. On the other hand, if only one MOSFET is needed, n-type MOSFET is superior to p-type MOSFET. After an extensive search, BSS83 is found as a small signal MOSFET model. However, it is still different from the n-type MOSFET used in the lab. Therefore, we need to modify its model for the analog circuits. On the other hand, default device model can be used for digital or switch circuits. Locate BSS83 is in the library of ‘PHIL_FET’, and place it in your design schematic sheet. Use the left mouse button to highlight it, and then click the right mouse button, a menu will appear. Select ‘Edit PSpice Model’, and then the model will appear in a pop-up window. Now change some of the parameters as the ones listed in the appendix, and then save it. If you are working in the same design, you don’t need to do this for every MOSFET, and they are automatically modified. However, if you open a new design, you need to modify the model again. 1) I-V Curve of NMOS 1 Simulate circuit 1 with DC sweep (the PSpice model of the MOSFET needs to be modified as mentioned above), the primary sweep is the drain-source voltage V2 (0 to 12V, increment 0.1V), the secondary sweep is the gate-source voltage V1 (0 to 12V, increment 2V). Label the curves with the corresponding gate voltages (or gate-to-source voltage), and compare it with the graph in the datasheet. 2) NMOS Transmission Gate MOSFET can be used as a switch, with different gate voltage the ‘switch’ can be closed or opened. Such a gate is called passing gate or transmission gate. Circuit 2 is an NMOS transmission gate. First, change the gate bias voltage to 0 V, observe the output. Then change the gate voltage to 5 V, the gate is supposed to be in the conducting mode; but you can see that the output signal is a little different from the input signal. What is it and why? 3) PMOS Transmission Gate Circuit 3 is a PMOS transmission gate. First, set the gate bias voltage to 5 V, and observe the output signal. Then change the gate voltage to 0 V, the gate is supposed to be in the conducting mode; but you can see it also has some problem in the output signal versus the input signal. Is it the same problem with NMOS transmission gate and why? 4) CMOS Transmission Gate Circuit 4 is a CMOS transmission gate. The gate voltage in the circuit is the non-conducting mode; compare the output signal and the input signal. Does it has the same problem with NMOS or PMOS transmission gates and why? 5) NMOS Inverters In MOSFET digital integrated circuit, the load of logic components is often the gates of a group of MOSFET, which is equivalent to a capacitor. Circuit 5 is an NMOS inverter. The input is a raised square wave (high 5V, low 0V, 1 kHz), find the relationship between the output and input voltages. Now increase the frequency (reduce the time intervals of the signal source parameters), observe the output signal and find the frequency such that the inverter does not operate properly. 6) CMOS Inverters Circuit 6 is a CMOS inverter. Start from the highest frequency obtained in the step above, does it work in this case? Now increase the frequency again, observe the output and find the highest frequency it can work. Compare with the NMOS inverter, what conclusion can be drawn? 7) NMOS Amplifier Circuit 7 is a simple common source NMOS Amplifier. Design the value of the resistors R1, R2, and R3, such that the voltage gain can be greater than 10 V/V, and the DC voltage at the drain of the NMOS is at 6 V. As the gate does not draw in any current (approximately), the values of R1 and R2 can be quite high (~ 1 M). The gate bias voltage is very important, as it controls the current in the MOSFET. There are two different approaches: one of them uses pretty high gate voltage and low R3, the other uses relatively low gate voltage (e.g. just 0.2V higher than the threshold voltage) and high R3. Which approach has high voltage gain and why? 8) (Milestone) NMOS Amplifier with Capacitive Load 2 0 V V 2 5 V d c 0 M 4 B S S 8 3 / P L P 4 2 3 0 V 1 T D = 0 . 5 m T F = 0 . 1 m P W = 0 . 4 m P E R = 1 m V 1 = 5 T R = 0 . 1 m V 2 = 0 V C 1 1 0 n1 2 M 3 B S S 8 4 / P L P 1 2 3 0  Circuit 5. NMOS Inverter V4 5Vdc C1 0.01u1 2 M1 BSS83/PLP4 2 3 V R1 1k 2 1 V3 TD = 0.5m TF = 0.1m PW = 0.4m PER = 1m V1 = 0 TR = 0.1m V2 = 5 0 V  Circuit 6. CMOS Inverter V4 5Vdc C1 0.01u1 2 M1 BSS83/PLP4 2 3 V V3 TD = 0.5m TF = 0.1m PW = 0.4m PER = 1m V1 = 0 TR = 0.1m V2 = 5 0 V M2  Circuit 7. NMOS Amplifier 0 V C 1 1 u F 1 2 R 3 2 1 V 1 F R E Q = 1 k V A M P L = 3 0 m V V O F F = 0 R 2 2 1 V 2 1 0 V d c R 1 2 1 0 M 1 B S S 8 3 / P L P 4 2 3  Circuit 8. NMOS Amplifier with Capacitive Load 5 R2 2 1 V R3 2 1 C1 10n 1 2 R1 2 1 C2 10n1 2 V1 10mVac 0Vdc 0 V2 10Vdc M1 BSS83/PLP 4 2 3 0 8. Appendices I. Modification of Device Model for NMOS in ALD1101: -----------------------------------------------------------------------  W = 6E-4 (channel width)  VTO=0.7 (threshold voltage)  VMAX=2.2E5 (maximum drift velocity)  THETA = 0.1 (mobility modulation parameter) ----------------------------------------------------------------------- II. Modification of Device Model of NMOS in CD4007 -----------------------------------------------------------------------  W = 4.5E-5 (channel width)  VTO=1.6 (threshold voltage)  THETA = 0.1 (mobility modulation parameter) ----------------------------------------------------------------------- 6