MOSFET Digital Channels - Lecture Slides | EE 334, Study notes of Electrical and Electronics Engineering

Download MOSFET Digital Channels - Lecture Slides | EE 334 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 Chapter 16 CMOS Inverter Chapter 16.3 p-Channel MOSFET pp n p n In p- channel enhancement device. A negative gate- to- source voltage must be applied to create the inversion layer, or channel region, of holes that, “connect” the source and drain regions. The threshold voltage VTP for p- channel enhancement-mode device is always negative and positive for depletion-mode PMOS. p-Channel MOSFET Cross-section of p-channel enhancement mode MOSFET 2 Complementary MOS CMOS The most abundant devices on earth Although the processing is more complicated for CMOS circuits than for NMOS circuits, CMOS has replaced NMOS at all level of integration, in both analog and digital applications. The basic reason of this replacement is that the power dissipation in CMOS logic circuits is much less than in NMOS circuits. CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratio less Always a path to VDDor GND in steady state low output impedance (output resistance in kΩ range) large fan-out. Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors In the fabrication process, a separate p-well region is formed within the starting n- substrate. The n- channel MOSFET is fabricated in the p- well region and p- channel MOSFET is fabricated in the n- substrate. CMOS Inverter Steady State Response VDD Rn VOut = 0 VIn = V DD VDD Rp VOut = VDD VIn = 0 CMOS Inverter DDOH OL VV V = = 0PMOS NMOS PMOS NMOS 5 from below graph vOPt or from above graph vONt vIt B C NMOS: nonsaturation PMOS: off NMOS: nonsaturation PMOS: saturation NMOS: saturation PMOS: saturation NMOS: saturation PMOS: nonsaturation NMOS: off PMOS: nonsaturation 6 Example 16.9 p1041 vIt vOPt vONt For VDD=5V Example 16.9 p1041 vIt vOPt vONt vOPt vONt vIt VDD=5V VDD=10V The transistor KN is also known as “pull down” device because it is pulling the output voltage down towards ground. The transistor KP is known as the “pull up” device because it is pulling the output voltage up towards VDD. This property speed up the operation considerably. The static power dissipation during both extreme cases (logic 1 or 0) is almost zero because iDP= iDN= 0. 10 01 VOutVIn CMOS inverter: series combination of PMOS and NMOS To form the input, gates of the two MOSFET are connected. To form the output, the drains are connected together. (ideal case) Ideally, the power dissipation of the CMOS inverter is zero. Practical device CMOS inverter (∼ nW) NMOS inverter (∼mW) CMOS Inverter in either High or Low State 7 CMOS Inverter Design Consideration The CMOS inverter usually design to have, This can achieved if width of the PMOS is made two or three times than that of the NMOS device. This is very important in order to provide a symmetrical transition, results in wide noise margin. But (because µN>µP) (1) (2) TPTN VV =      =      L Wk L Wk PN '' '' PN kk > How equation (2) can be satisfied ? NMOS: nonsaturation PMOS: off NMOS: nonsaturation PMOS: saturation NMOS: saturation PMOS: saturation NMOS: saturation PMOS: nonsaturation NMOS: off PMOS: nonsaturation Symmetrical Properties of the CMOS Inverter vOPt vONt 2 DD It VV = 10 CMOS inverter currents When NMOS transistor is biased in the saturation region The current in the inverter is controlled by vGSN and the PMOS vSDP adjusts such that iDP = iDN . As long as NMOS transistor is biased in the saturation region the square root of the inverter current is linear function of the input voltage. CMOS inverter currents When PMOS transistor is biased in the saturation region The current in the inverter is controlled by vSGP and the NMOS vDSN adjusts such that iDP = iDN . As long as PMOS transistor is biased in the saturation region the square root of the inverter current is linear function of the input voltage. NMOS: saturation PMOS: saturation NMOS: off PMOS: nonsaturation NMOS: saturation PMOS: nonsaturation CMOS inverter currents NMOS: nonsaturation PMOS: off NMOS: nonsaturation PMOS: saturation Problem 16.33 p1102 (a) (b) 11 Power Dissipation There is no power dissipation in the CMOS inverter when the output is either at logic 0 or 1. However, during switching of the CMOS inverter from low logic 0 to logic 1, current flows and power is dissipated. Usually CMOS inverter and logic circuit are used to drive other MOS devices by connecting a capacitor across the output of a CMOS inverter. This capacitor must be charged and discharged during the switching cycle. Triode Region NMOS Transistor Capacitances Cox” = Gate-Channel capacitance per unit area(F/m2) CGC = Total gate channel capacitance CGS = Gate-Source capacitance CGD = Gate-Drain capacitance CGSO and CGDO = overlap capacitances (F/m) Saturation Region NMOS Transistor Capacitances Drain is no longer connected to channel. Cutoff Region NMOS Transistor Capacitances Conducting channel region is completely gone. CGB = Gate-Bulk capacitance CGBO = Gate-Bulk capacitance per unit width. 12 VDD Rn Vout CL VIn = VDD VDD Rp Vout CL VIn = 0 Gate response time is determined by the time to charge CL through Rp (discharge CL through Rn) Switch Model of Dynamic Behavior CMOS Inverter Power has three components Static power: when input isn’t switching Dynamic capacitive power: due to charging and discharging of load capacitance Dynamic short-circuit power: direct current from VDD to Gnd when both transistors are on CMOS Inverter Power Static current: in CMOS there is no static current as long as VIn < VTN or VIn > VDD+VTP Leakage current: determined by “off” transistor Influenced by transistor width, supply voltage, transistor threshold voltages VDD VI<VTN Ileak,N VDD VDD Ileak,P Vo(low) VDD Static Power Consumption CMOS Inverter Power Case I: When the input is at logic 0 PMOS is conducting and NMOS is in cutoff mode and the load capacitor must be charged through the PMOS device. Power dissipation in the PMOS transistor; PP=iLVSDp= iL(VDD-VO) The current and output voltages are related by, iL=CLdvO/dt Similarly the energy dissipation in the PMOS device can be written as the output switches from low to high, 2 2 0 2 0 0000 2 1 )0 2 ()0(, 2 ,)( DDLP DD LDDDDLP V O L V ODDLP O V OL V ODDLP O ODDLPP VCE VCVVCECVCE dCdVCEdt dt dVCPE DD DD DDDD = −−−=−= −=−== ∫∫∫∫ ∞∞ ν ν ννννν Dynamic Capacitive Power and Energy stored in the PMOS CMOS Inverter Power the energy stored in the capacitor CL when the output is high.