Download MOSFET Small Signal Model and Analysis - Lecture Slides | ECE 3040 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! ECE 3040 - Dr. Alan DoolittleGeorgia Tech MOSFET Small Signal Model and Analysis •Just as we did with the BJT, we can consider the MOSFET amplifier analysis in two parts: •Find the DC operating point •Then determine the amplifier output parameters for very small input signals. ECE 3040 - Dr. Alan DoolittleGeorgia Tech MOSFET Small Signal Model and Analysis Linear Two Port Network + V1 - i1 i2 + V2 - I1=y11V1 + y12V2 I2=y21V1 + y22V2 General “y-parameter” Network Non-Linear I-V relationship (BJT, MOSFET, etc…) + V1 - i1 i2 + V2 - Linearize over “small signal range” IGS=y11VGS + y12VDS IDS=y21VGS + y22VDS MOSFET “y-parameter” Network vGS vDS iDS iGS ECE 3040 - Dr. Alan DoolittleGeorgia Tech MOSFET Small Signal Model and Analysis Putting the mathematical model into a small signal equivalent circuit Compare this to the BJT small signal equivalent circuit ECE 3040 - Dr. Alan DoolittleGeorgia Tech MOSFET Small Signal Model and Analysis Example: Jaeger 13.94 Calculate the voltage gain, Av=vo/vs Given: Kn=1 mA/V2 , λ=0.015 V-1 Bias Point of: IDS=2 mA, VDS=7.5V ECE 3040 - Dr. Alan DoolittleGeorgia Tech MOSFET Small Signal Model and Analysis Example: Jaeger 13.94 ( )2 2 TGS n o VV K g −= λ ( )( )DSTGSnm VVVKg λ+−= 1 Need to find VGS-VT ( )[ ]( ) ( )[ ]( ) Ω=⇒==∴ ==− +−= +−= krSgmSg VVV VV VmA mA VVV K I oom TNGS TNGS DSTNGS n DS 9.361.2711.2 9.1 11.1 4 )5.7(015.01 2 /1 2 1 2 2 2 2 µ λ ECE 3040 - Dr. Alan DoolittleGeorgia Tech MOSFET Small Signal Model and Analysis Complete Model of a MOSFET Reverse Bias Junction capacitances Overlap of Gate Oxide and Gate to channel capacitance Overlap of Gate Oxide Gate to channel to Bulk capacitance FSB mmb V gg φ γ 22 + = Due to effective modulation of the threshold voltage. ECE 3040 - Dr. Alan DoolittleGeorgia Tech MOSFET Small Signal Model and Analysis SPICE MOSFET Model SPICE models the drain current ( IDS ) of an n-channel MOSFET using the following parameters/equations (SPICE variables are shown in ALL CAPPITAL LETTERS) Cutoff: IDS = 0 Linear: Saturation: Threshold Voltage: Channel Length LEFF=L-2LD ( )[ ] ( )( )DSDSGSDS EFF DS VLAMBDAVVTHVVL WKP I +−− = 12 2 ( )[ ] ( )( )DSGS EFF DS VLAMBDAVTHVL WKP I +− = 1 2 2 ( )PHIVPHIGAMMAVTOV BSTH 22 −−+= ECE 3040 - Dr. Alan DoolittleGeorgia Tech MOSFET Small Signal Model and Analysis SPICE MOSFET Model – Additional Parameters SPICE takes many of it’s parameters from the integrated circuit layout design: L W AD=WxLdiff(drain) Ldiff(drain) Ldiff(source) AS=WxLdiff(source) Source Gate Drain L = polysilicon gate length W = polysilicon gate width AD = drain area AS = source area PD = perimeter of drain diffusion (not including edge under gate) PS = perimeter of source diffusion (not including edge under gate) NRD = number of “squares” in drain diffusion NRS = number of “squares” in source diffusion PS=2xLdiff(source)+W PD=2xLdiff(drain)+W Specified in terms of the minimum feature size
