ECEN5355 Lecture #37: MOSFET Technology and Memory Circuits - Prof. Wj Park, Study notes of Electrical and Electronics Engineering

Download ECEN5355 Lecture #37: MOSFET Technology and Memory Circuits - Prof. Wj Park and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! © Bart Van Zeghbroeck, 2005ECEN5355 Lecture # 37 Lecture #37:MOSFET technology Poly-silicon gate technology Self-aligned gate Low doped drain (LDD) LOCOS Isolation Field and channel implants MOSFET Memory circuits © Bart Van Zeghbroeck, 2005ECEN5355 Lecture # 37 1970’s MOSFET Process Lithography step Process step Process 1. Field oxide growth Oxide etch Source-drain diffusion Thermal oxidation HF etch Boron diffusion 2. Oxide etch Gate oxide growth HF etch Thermal oxidation 3. Via hole etch HF etch 4. Aluminum metal deposition Aluminum etch Contact anneal and surface state reduction Evaporation Wet chemical etch Furnace anneal in H2/N2 © Bart Van Zeghbroeck, 2005ECEN5355 Lecture # 37 MOSFET Process evolution Initial process and process parameters Current process and process parameters 10 μm gate length 0.1 μm gate length 1 inch wafers 300 mm wafers 2 x 2 mm chips 1 x 2 cm chips Thermal oxidation CVD deposition Field oxide isolation LOCOS isolation, trench isolation Wet chemical etching Reactive ion etching (RIE) Diffusion Ion implantation PMOS nMOS, CMOS Enhancement load, resistor load Depletion load, complementary load Aluminum gate Poly-silicon/Silicide self-aligned gate Evaporated aluminum wiring with 2% copper Sputtered copper One or two metal wiring levels without planarization Up to six wiring levels with planarization and tungsten plugs Metal evaporation Sputtering Hydrogen anneal Deuterium anneal © Bart Van Zeghbroeck, 2005ECEN5355 Lecture # 37 Self-aligned Poly-Silicon Gate MOSFET p-substrate Poly-silicon gate Photo resist n+n+ Phosphorous Implant © Bart Van Zeghbroeck, 2005ECEN5355 Lecture # 37 Self-aligned Poly-Silicon Gate MOSFET p-substrate Source Drain SiO2SiO2 Shallow implant Poly-silicon Gate n+ n+ Deep implant © Bart Van Zeghbroeck, 2005ECEN5355 Lecture # 37 Poly-Silicon Gate Flatband Diagram E Ec EF Ev Poly-silicon Semiconductor Evacuum χq Oxide oxideq χ qVFB χq © Bart Van Zeghbroeck, 2005ECEN5355 Lecture # 37 Workfunction difference )ln( ,, a polya tSpoly N N V=Φ Poly-silicon gate p-type poly-silicon gate n-type poly-silicon gate )ln( , 2 , apolyd i tSpoly NN nV=Φ © Bart Van Zeghbroeck, 2005ECEN5355 Lecture # 37 Memory Addressing Memory cell Memory cell Memory cell Memory cell Word lines Bit lines Sense Amplifiers