MSI Building Blocks - Design Automation of Embedded Systems - Lecture Slides, Slides of Computer Science

Download MSI Building Blocks - Design Automation of Embedded Systems - Lecture Slides and more Slides Computer Science in PDF only on Docsity! 12/8/2002 2 Unit 8 EE 510 MSI Building Blocks Docsity.com 12/8/2002 3 Topics to be Covered ◆ In this lecture we will cover the following set of basic combinational building blocks: – Multiplexers (MUXs) and demultiplexers (DMUXs). » As a result, define ACTIVE HIGH and ACTIVE LOW terminology. – Encoders – Decoders – ROMs Docsity.com 12/8/2002 6 Terminology ◆ The terms ACTIVE and INACTIVE are used throughout the digital area. ◆ They are supported by Institute of Electrical and Electronic Engineers (IEEE), the largest such professional group in the world. ◆ These terms are also frequently used in manufacturers data books. Docsity.com 12/8/2002 7 Terminology ◆ A state is said to be ACTIVE if it is the condition for causing something to happen. And for every ACTIVE state there must exist one that is INACTIVE. ◆ In the binary system, these descriptors take the logic values: – ACTIVE = logic 1 – INACTIVE = logic 0 Docsity.com 12/8/2002 8 Positive and Negative Logic ◆ In the positive logic system, we associate the physical voltage levels with the logic domain values as follows: High Voltage (+5v) Logic 0 Low Voltage (0v) Logic 1 ◆ In the negative logic system, we associate the physical voltage levels with the logic domain values as follows: High Voltage (+5v) Logic 1 Low Voltage (0v) Logic 0 Docsity.com 12/8/2002 11 Documentation Standards Active Levels ◆ Each signal name should have an active level associated with it. ◆ A signal is active high if it performs the named action or denotes the named condition when it is HIGH or 1. ◆ A signal is active low if it performs the named action or denotes the named condition when it is LOW or 0.. Docsity.com 12/8/2002 12 Documentation Standards Active Levels ◆ A signal is said to be asserted when it is at its active level. ◆ A signal is said to be negated or deasserted when it is not at its active level. ◆ The active level of each signal in a circuit is normally specified as part of its name, according to some convention. Docsity.com 12/8/2002 13 Documentation Standards Active Levels Active Low Active High READY- READY+ ERROR.L ERROR.H ADDR15(L) ADDR15(H) RESET* RESET ENABLE~ ENABLE /TRANSMIT TRANSMIT Different Naming Conventions Naming convention must be compatible with the input requirements of and CAD tools. Docsity.com 12/8/2002 16 Why have ACTIVE LOW? ◆ By now, this question should have formed in your mind. It is tied up with power consumption, and requires that we return to a transistor level description of the output stage of (for example) a TTL gate: Vcc RL IL Vin Vout Docsity.com 12/8/2002 17 Why ACTIVE LOW? ◆ When Vin turns the transistor ON, the collector voltage drops to ~0.7V, and current flows from Vcc into the ground, dissipating heat in RL. ◆ The power dissipated is approximately Vcc2/RL. ◆ When Vin turns the transistor OFF, Vout rises to Vcc, the current through RL is negligible, and no power is dissipated in RL. Vcc RL IL Vin Vout ◆ When a circuit is not to be used for long periods of time, leave it in the Vout high (logic 1) state, and assert the logic 0 state for the short time needed to activate it. Docsity.com 12/8/2002 18 Design of a MUX ◆ First, let us consider a small 4-to-1 MUX. This has 2 select lines. The truth table appears as follows: 0 1 2 3 n F I0 I1 I2 I3 2 S0-S1/EN EN S1 S0 F 0 x x 0 1 0 0 I0 1 0 1 I1 1 1 0 I2 1 1 1 I3 F = (S1’S0’I0 + S1’S0I1 + S1S0’I2 + S1S0I3)EN’ Docsity.com 12/8/2002 21 Designing with a MUX F A B C m( , , ) ( , , , )= ∑ 0 2 5 7 1 /EN 0 1 2 3 F 3 A,B,C 4 5 6 7 0 1 0 0 1 0 1 0 A B C F 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 Docsity.com 12/8/2002 22 Using a 3-to-8 MUX with 4 input variables F A B C D m( , , , ) ( , , , , , , , , , )= ∑ 3 4 5 6 7 9 10 12 14 15 0 /EN 0 1 2 3 F 3 A,B,C 4 5 6 7 D 1 1 D D' D' 1 A B C D F 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 Docsity.com 12/8/2002 23 DECODERS ◆ A DECODER is an n-input/2n- output combinational logic device which has the function of activating one of its 2n outputs for every unique input pattern (or WORD) of n bits. ◆ Each output is identified by the MINTERM CODE, mi, of the input WORD pattern it represents. 0 1 2 3 2 A1-A0 Y0 Y1 Y2 Y3 Docsity.com 12/8/2002 26 Design of a Commercial Decoder ◆ Implementation of a 2-to- 4 decoder. This has ACTIVE LOW ENABLE and ACTIVE LOW OUTPUTs. /Y0 A1 /EN /Y1 /Y2 /Y3 A0 Docsity.com 12/8/2002 27 Designing with Decoders ◆ Since each output is identified by the MINTERM CODE, combinational circuits can be implemented by ORing the appropriate outputs together. 0 1 2 3 4 5 6 7 3 FA2 - A0 /EN F m= ∑ ( , , , )0 2 5 7 Docsity.com 12/8/2002 28 DEMULTIPLEXERs (DMUXs) ◆ A DEMULTIPLEXER is a device with – 1 data input – n data select lines – 2n output lines – which can route data from the single input source to one of several destinations. Y0 Y1 Y2 Y3 0 1 2 3 /EN S0S1 SELECT LINES Docsity.com 12/8/2002 31 DMUX from a DECODER ◆ Shown here is the alternative view of a DECODER as a DMUX. ◆ It is left to you to determine what further gates are needed (if any) when utilizing a commercial DECODER/DMUX chip. remember that these usually have an ACTIVE LOW ENABLE and ACTIVE LOW OUTPUTs. 0 1 2 3 4 5 6 7 A2 - A0 EN 3 Docsity.com 12/8/2002 32 Read-Only Memory (ROM) ◆ ROMs belong to an important class of general-purpose IC logic array devices which find extensive use in combinational logic design. ◆ We met the use of ROMs in combinational logic design in Lecture 1. Here we shall examine the logic structure of a ROM. Docsity.com 12/8/2002 33 ROM Logic Structure ◆ A ROM is an n-input/m-output device, composed of a DECODER stage and a “memory” array. ◆ Bit combinations of n input variables are called addresses. 0 1 2 3 3 A2 - A0 Ym-1 Y1 Y0 Fusible Links 2**n-1 2**n-2 n-input OR gate ◆ There are 2n possible addresses each representing a coded MINTERM on the output side of the DECODER stage. ◆ To program, the fusible links are “blown: to remove the connection. Docsity.com 12/8/2002 36 Structural Diagram of a ROM ◆ Use this symbol whenever you need to draw a ROM in your logic diagram. It is far more expressive than a rectangular box with the name ROM (or DECODER or MUX) plastered somewhere near the box. n m Address Inputs Data Outputs Docsity.com 12/8/2002 37 What have we covered in this lecture? ◆ We have looked at a small selection of MSI combinational logic devices. ◆ We examined MUXs, what they do, how they are constructed, and how they are used. ◆ We examined DECODERs, what they do, how they are constructed, and how they are used. ◆ We saw how to use decoders as DMUXs. Docsity.com 12/8/2002 38 What have we covered in this lecture? ◆ We revisited ROMs, to see how they are constructed. We saw in Lecture 2 how to use ROMs in combinational design. ◆ Read the textbooks and my book for additional information. ◆ Think about your preferred grading option and project ◆ Write me about your project ideas Docsity.com