multicycle_datapath deals with the multicycle implementation of processor, Lecture notes of Advanced Computer Architecture

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Datapath with Control III Shift left 2 PC Instruction memory Read address Instruction [31– 0] Data memory Read data Write data Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Instruction [15– 11] Instruction [20– 16] Instruction [25– 21] Add ALU result Zero Instruction [5– 0] MemtoReg ALUOp MemWrite RegWrite MemRead Branch Jump RegDst ALUSrc Instruction [31– 26] 4 M u x Instruction [25– 0] Jump address [31– 0] PC+4 [31– 28] Sign extend 16 32 Instruction [15– 0] 1 M u x 1 0 M u x 0 1 M u x 0 1 ALU control Control Add ALU result M u x 0 1 0 ALU Shift left 2 26 28 Address 31-26 25-0 opcode addressJump MIPS datapath extended to jumps: control unit generates new Jump control bit New multiplexor with additional control bit Jump Composing jump target address Example: Fixed-period clock vs. Variable period clock in a single-cycle implementation  Consider a machine with an additional floating point unit. Assume functional unit delays as follows  memory: 2 ns., ALU and adders: 2 ns., FPU add: 8 ns., FPU multiply: 16 ns., register file access (read or write): 1 ns.  multiplexors, control unit, PC accesses, sign extension, wires: no delay  Assume instruction mix as follows  all loads take same time and comprise 31%  all stores take same time and comprise 21%  R-format instructions comprise 27%  branches comprise 5%  jumps comprise 2%  FP adds and subtracts take the same time and totally comprise 7%  FP multiplys and divides take the same time and totally comprise 7%  Compare the performance of (a) a single-cycle implementation using a fixed- period clock with (b) one using a variable-period clock where each instruction executes in one clock cycle that is only as long as it needs to be (not really practical but pretend it’s possible!)  Note particularities of multicyle vs. single- diagrams  single memory for data and instructions  single ALU, no extra adders  extra registers to hold data between clock cycles Multicycle Approach PC Instruction memory Read address Instruction 16 32 Add ALU result M u x Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 Shift left 2 4 M u x ALU operation3 RegWrite MemRead MemWrite PCSrc ALUSrc MemtoReg ALU result Zero ALU Data memory Address Write data Read data M u x Sign extend Add PC Memory Address Instruction or data Data Instruction register Registers Register # Data Register # Register # ALU Memory data register A B ALUOut Single-cycle datapath Multicycle datapath (high-level view) Multicycle Datapath Shift left 2 PC Memory MemData Write data M u x 0 1 Registers Write register Write data Read data 1 Read data 2 Read register 1 Read register 2 M u x 0 1 M u x 0 1 4 Instruction [15– 0] Sign extend 3216 Instruction [25– 21] Instruction [20– 16] Instruction [15– 0] Instruction register 1 M u x 0 3 2 M u x ALU result ALU Zero Memory data register Instruction [15– 11] A B ALUOut 0 1 Address Basic multicycle MIPS datapath handles R-type instructions and load/stores: new internal register in red ovals, new multiplexors in blue ovals  Our goal is to break up the instructions into steps so that  each step takes one clock cycle  the amount of work to be done in each step/cycle is about equal  each cycle uses at most once each major functional unit so that such units do not have to be replicated  functional units can be shared between different cycles within one instruction  Data at end of one cycle to be used in next must be stored !! Breaking instructions into steps  Read registers rs and rt in case we need them. Compute the branch address in case the instruction is a branch.  RTL: A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC + (sign-extend(IR[15-0]) << 2); Step 2: Instruction Decode and Register Fetch (ID)  ALU performs one of four functions depending on instruction type  memory reference: ALUOut = A + sign-extend(IR[15-0]);  R-type: ALUOut = A op B;  branch (instruction completes): if (A==B) PC = ALUOut;  jump (instruction completes): PC = PC[31-28] || (IR(25-0) << 2) Step 3: Execution, Address Computation or Branch Completion (EX)  Again depending on instruction type:  Loads and stores access memory  load MDR = Memory[ALUOut];  store (instruction completes) Memory[ALUOut] = B;  R-type (instructions completes) Reg[IR[15-11]] = ALUOut; Step 4: Memory access or R-type Instruction Completion (MEM) Multicycle Execution Step (1): Instruction Fetch IR = Memory[PC]; PC = PC + 4; 4 PC + 4 Multicycle Execution Step (2): Instruction Decode & Register Fetch A = Reg[IR[25-21]]; (A = Reg[rs]) B = Reg[IR[20-15]]; (B = Reg[rt]) ALUOut = (PC + sign-extend(IR[15-0]) << 2) Branch Target Address Reg[rs] Reg[rt] PC + 4 Multicycle Execution Step (3): Memory Reference Instructions ALUOut = A + sign-extend(IR[15-0]); Mem. Address Reg[rs] Reg[rt] PC + 4 Multicycle Execution Step (3): Jump Instruction PC = PC[31-28] concat (IR[25-0] << 2) Jump Address Reg[rs] Reg[rt] Branch Target Address Multicycle Execution Step (4): Memory Access - Read (lw) MDR = Memory[ALUOut]; Mem. Data PC + 4 Reg[rs] Reg[rt] Mem. Address Multicycle Execution Step (4): Memory Access - Write (sw) Memory[ALUOut] = B; PC + 4 Reg[rs] Reg[rt]