Nintendo Wii type - Microcomputer Applications - Exam, Exams of Microcomputers

Download Nintendo Wii type - Microcomputer Applications - Exam and more Exams Microcomputers in PDF only on Docsity! 1 MIAP E3001 CORK INSTITUTE OF TECHNOLOGY INSTITIÚID TEICNEOLAÍOCHTA CHORCAÍ Module Title: Microcomputer Applications Module Code: MIAP E3001 School: Electrical and Electronic Engineering Programme Title: Bachelor of Engineering in Applied Electronics Design – Award Bachelor of Engineering in Automation and Control – Award Bachelor of Engineering in Communications Systems - Award Programme Code: EAELN_7_Y3 EELAR_7_Y3 ECOSY_7_Y3 EAELD_7_Y3 External Examiner(s): Mr. David Denieffe, Dr Paula O Sullivan Internal Examiner(s): Mr. Fergus O Reilly Instructions: Answer THREE questions. All questions carry equal marks. Duration: 2 HOURS Sitting: Winter 2007 Requirements for this examination: Note to Candidates: Please check the Programme Title and the Module Title to ensure that you have received the correct examination paper. If in doubt please contact an Invigilator. 2 MIAP E3001 Q1 (a) Why might you use a micro-controller instead of a micro-processor? What features does a micro-controller have over a micro-processor? What advantages, disadvantages does each have? [8 marks] (b) You have the following selection of micro-processors/micro-controllers available to you for a number of projects: (i) Low Power High Speed Motorola 68000 Family (40MHz), (ii) Microchip PIC 16c74 (4 MHz), (iii) AMD/Intel Pentium Clone (500 MHz), (iv) Analog Devices 8051(2MHz) compatible micro-controller. For each of the following applications identify (i) Approximate number of Input & Outputs (ii) Estimate of speed/performance required. (iii) Complexity/Range of algorithms/programmes to execute. Applications: • Nintendo Wii type home games console • 3G Mobile phone with camera • Bed-side Digital Clock Choose one of the above processors for each application saying why you think it is appropriate to the application. [16 marks] (c) As a member of an 8-bit micro-processor usage team, you are tasked to devise a scheme to vary the number of special registers from 200 (basic model) to 400(advanced model), while being restricted to using only 8 bits(max of 256) to describe which register is in use. (i) Can you describe a scheme to do this? [6 marks] (ii) Which micro-processors/micro-controller currently make use of such a technique? [4 marks] [Total: 34 marks] PIC16C63A/65B/73B/74B PIC16C63A/65B/73B/74B TABLE 4-1; SPECIAL FUNCTION REGISTER SUMMARY TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Pemsc shes, | nesers® [Banko F Bank 1 ay fet aeneseang tus neaton ues cnvanrs cr ESK tn adaees data memory (nat anmscal enter) neon yean acca anna] | nor ressing hs locaton uses contents of FSR toa ata memory (nota physical register) ain 7 Fimers moauesreaiter Se mion_ReG| REPU | wreos | Tocs P Ps psi_ [Pst mnafrin aay aan ecu Program Councers Pc) Least Sionmean: Bvie see 9809 9000 one) 220 Poult |Prearam counters (PC) Lea e pen [see [ar [a [mo | to Oe econ wewe ote gana] [6% [stares [eet [ees Ty z 2c] aa fe rcract ara memory AaAF=SE peter once wor amen va] [8th | FSR Inciect data memory adaress potter ¥ ein PORTA PORTA Maks | itd wtaen wren PORTA pins winan rosa eonoy eu anna) Be JOR TA Data Direction Flagiat 2 aaa a 1212) ara [Porte [PORTO Cata Laten wren witen: PORTS ps when read on ec waa) " [PORTC Data Drecton re anf a) sox [PorTO® [PORTO Cata Laton wren writen: PORTO pins wen re rane nn ML n ISD® | PORTO Data Drection te gaat[siay aaa ba frorre? P= | = [= [2 RE REE cen] | aise F 5 z TE Data Brecon ul Ab PCLATH!! — — = Mile Buffer far the upper 5 bits uf tae Program Counler =--8 guna ---0 ovua| “A P Hn nite nt ne unite orn farce? | cir | pee | Tor PRIF THF NTF RRIF coy aco aren ona] (868 | INTCON®) eI c ae | NTE | ROVE or | NTF | RG ach eID psi) | apne) KC UIE SSKIF CORTIF LEHIIF IMATE pcan anaa area anna] ach PIE: et oe" RCIE THE SPIE, iE MR2IE | TMRIE avn = = = = = = = CORE = g0n PIE IE er lang rege orne Leas Sign neat ce oe cbt TR regs mon san uta wana] [60 [PCON FOR arn ang recserorine hos Sqn cant the Je-DE TOR riser von soos su [unimiemenies ic 5 = [Tickst] tickrse Tioscen TIEYNG TMRIGS TMRION yey ne ee unimptemented in woo | sorev | ssren | cnr SANG econ 2000 aveo onea] (sim [ssesiar | | i ait [va [er ceotvercempars on Reiser ALSO) waar nee au aa] _| 8H Crimpers [ én ecrria — [eariowScmpaciPWN Rosi ce eee soc ews] | [unmperenie mm focmcon | = | = | comix | cory coms fen sean vo cu anna) [57 le cere ; is JUSAKI Iransmit Vata register 9690 9699 9¢60 o009) |: 8 [Baud Rate Generator registe! an USART Recehve Data ‘eister on 3000 oto 0909 [unmpemenies con [ecrrat _|eanteroemparsirnn Rea Tava ww] [280 [unimptementea can Jecrnai — [cavkowScmpaciPWN Rosi ces case sec waa} [8D rimperenied | on forrscon | = | = | cenax | corey cara acre cara ecrem an anny =-cn oma] [608 [unmpementea fen woo” [avesr | cess | ons | cms nwo saben AON wean 90 9 900 v9 9 7 Per z= Tegerid x = unk w = unchanged, q= vale dedands on Soalion, -= uninplemered, ead as 0 epands on bnted, read Share Ieations are nimlerentac, enc 98°C edas Note 1: ‘Tro upper byt of tho program counters aot dct accoesble. PCLATH is hosing “git forthe PC~12.8= isnot dectly accessible. PCLATH is a holding 2 2: [he IP and XI os ore reserved anos mona ese bs es maintain tho 3: Other (oan pawar py RTSETS inure atornal RST trough CIR ara Watchdog Tinar Rast and Watchdog Time 42 Those registers can bo addrossed ‘rom ether bank, Si PORIO, POR |e and the purala slave porl wre nol implemented on registers 6: The VD is nat implomented on the PICIGCS30 we IC TECBS 738, abe cays maintain these ts and registors cles nian Uiese bis nd PIC16CB3AV72B; abv its and MIAP E3001 TABLE 11-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) ° (Asynchronous) Baud Rate = Fosc/(64(SPBRG+1)) Baud Rate = Fosci( 16(SPBRG+ 1)) 1 (Synchronous) Baud Rate = Fosci(4(SPBRG+1)) NIA TABLE 11-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on: Value on Address Name Bit7 Bité Bit5 Bit4 | Bit3 | Bit2 Bit1 Biro POR, all other BOR RESETS 98h TXSTA | CSRC [ TX9 | TXEN | SYNC = BRGH | TRMT | TX9D [ 0000 -010 | 0000 -010 18h RCSTA | SPEN RX9_| SREN | CREN - FERR | OERR | RX9D | 0000 -o0x | 0000 -00x 99h SPBRG | Baud Rate Generator register 0000 0000 | 0000 0000 Legend: x = unknown, - = unimplemented, read as ‘0. Shaded cells are not used by the BRG. REGISTER 12-1: ADCONO REGISTER (ADDRESS 1Fh) RW-0 RWO RW RAO RW.O RIO U0 RMW.O apcst | apcso | cHs2 [ cHsi [| cHso [GODONE] — ADON bit 7 bit O bit 7-6 ADCS1:ADCSO: A/D Conversion Clock Select bits 00 = Fosc/2 01= Fosc/é 10 = Fosc/a2 11 = FRc (clock derived from the internal A/D module RC oscillator) bitS-3 CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RAO/ANO) 901 = channel 1, (RAT/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RAS/ANS) 101 = channel 5, (REO/ANS)") 110 = channel 6, (RE1/ANS\() 111 = channel 7, (RE2/AN7)(1 bit2 GO/DONE: A/D Conversion Status bit IEADON = 1 D conversion in progress (setting this bit starts the A/D conversion) D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete) bit 1 Unimplemented: Read as '0' bit 0 ADON: A\D On bit AID converter module is operating AID converter module is shut-off and consumes no operating current Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16C74B only. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0 -n = Value at POR, 1’ = Bitis set O' = Bit is cleared x = Bitis unknown REGISTER 12-2: ADCON1 REGISTER (ADDRESS 9Fh) uU-0 U-0 U-0 U-0 U-0 R/W-O RW-0 R/W-O = = [= T= [T= PCFG2 | PCFG1 | PCFGO oit7 bitd bt 7-3 Unimplemented: Read as 0" bt 2-0 PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFGO| RAO | RA1 | RA2 | RAS | RAS | REO | RE) |/RE | Vrer 000 A A A A A A A A_[ Von 001 A A A A_| Veer [A A A_ | RA3 a10 A A A A A D. D D_ | voo on A A A A_| Veer [ D D D_ | RAS I) A A D D A D D D_ | Voo 101 A A D D | Veer | D D D_ | Ras 11x D D D D D D D D_ | Voo A= Analog input D = Digital /0 Note 1: REO, RE1 and RE2 are implemented on the PIC16C74B only. Legend: eacable bit Value at POR Writable bit U = Unmpiemented bit, read as ‘0’ Bit is set ‘0’ = Bit is cleared x = Bit is unknown