Nodal Analysis - Introduction to Microelectronic Circuits - Solved Exam, Exams of Microelectronic Circuits

Download Nodal Analysis - Introduction to Microelectronic Circuits - Solved Exam and more Exams Microelectronic Circuits in PDF only on Docsity! UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering Professor Oldham and Computer Sciences EECS 40 — FINAL EXAM Sele fou Ss Name: Guidelines: (a) One page of notes allowed (both sides). (b) You may use a calculator. (c) Do not unstaple the exam. 13 December 1999 Fall 1999 Student ID: TA: O Kusuma O Chang (d) Show all your work and reasoning on the exam in order to receive full or partial credit. (e) This exam contains 16 pages plus the cover page and 2 sheets of scratch paper included at the end of the exam. You can remove these from the rest of the exam if you wish. Problem Points Possible Your Score 1 20 25 30 25 25 20 25 col ral a} ul} alow] nr 30 Total 200 GWVsaE sy odal An: (a) Write 2 nodal equations sufficient to find voltages A and B. (b) The switch closes at tf = 0 (after a very long time open). Write 2 nodal differential equations describing V, and Vy. —at = 0 Ry Vi® 2%o Fa OOF L (c) What are the values of V,, Vv, att = 0* and t4 0? dy a Betore Switch iy closed, no Yoltrge acrss G and G@, We Luow Wltase Alito on ‘ Cop aci tor (S Conti nuns. be Vx (t=ot) = W (£20) = OV. Ag L i) QD, no Cunent flows thn Gq aud Cz . Ux (43 @) = VY (Lea)=V, 1of 16 Problem 2 Worksheet and Answers (a) FILL OUT A B C|G H Ty| DE Tg, WITH ZEROS oO 010 tle { ¢ AND ONES Oo 9 Tyetitetey fe Oo 1 0;o tlol¢ (tea Oo 1 tye pete tele ( 10 Ofeftel, [i fete 1 0 'feftejtiel fete 1 1 Ofe¢fefi ti fey? tol it fet i ftefe {te booth Correctly tmplement (b) T. Ves Function correct? ss| ves (yes or no?) Tee | ces (c) Delay SS Circuit Tor BB Circuit -NkWo 4 of 16 A A + B Cc Problem 3 Nerd Contest — Details (30 points) (Independent of Problem 2) (a) The schematic of a CMOS inverter analyzed in Lecture 25 is shown in the figure below. Note the unit gate delay is 16.5 ps when the inverter drives an identical inverter. Using the same CMOS technology, you are to design (that means draw the schematic of) a 2-input NAND gate [NOT Vpp = 18 Pee nk a layout please!]. Please size the devices for equal worst- 9 Ee case rise and fall times, and use 1.5/0.18 as the p-channel 0.69RC = 16.5ps device size. —d[_ 1570.18(um/pm) LT a (um/pm) (b) Find the input capacitance and the output resistance of such a NAND gate (worst case). Compute the gate delay assuming the NAND gate drives the inputs to identical NAND gates. Ignore drain-bulk and interconnect capacitance. (c) Now draw the schematic of the NOR gate and indicate device sizes needed to get equal (worst-case) rise and fall times. Again use 1.5/0.18 as the p-channel device size. (d) Find the input capacitance and the output resistance of such a NOR gate. Compute the unit gate delay assuming the NOR gate drives the inputs to identical NOR gates. Ignore drain-bulk and interconnect capacitance. Tor He Twertar tr the figure above, Ib.Bps = O.64RC DC= C Car+Cad = 16,5 ps / C0.84 ~8.1kQ) CG juan th 7 CC Maen Aven CPMOS = 2 Area CNMOS) Com = TDR Xk HD SIRF C0.15 um X 0. tam) Cae = T. TPR XE HS IAPR Ci Sum xX Oldcum ) ( Cb) Cen =S\ 1426 Cer = Gain Cf R= 3.1 lead T= O44 XR ( Can+Cer) =2opsec Bole ove W/le= 15/08) GC) Gey = (98h © batSun Oda, — Sank O\ar ) Cap = 5, |4RR R= 6.4kde T=0.64 xRX (Cant Cae) =21:S psec 5 of 16 (a) (b) (c) (d) Upp — W_o15 pmos W - 15. LO A— b-B NMos ¥ = 5 Vout ON AS [Rp = DRv BY \ Ww. LS = . MOS ONS schematic of NAND gate Cop = Di 14 {F Con = Ds |e R= | K Unit Gate Delay = __ 2 pS Vpp Woius A—4 pmos ¥ = 15 nos © . QS'15 tr Vout L O.v\ a ke ORp = IRs \ wy _ O.3ns = NMos & Sas schematic of NOR gate Cop = Bs (4 fF Con = 129 oF R=__ 6.2K UnitGateDelay = _— 27.5 ps 6 of 16 Selufeas Problem 5 Inverter Transient (25 points) Vv, Yop L 2.5V Cy = 0.1pF Rg = 500 T P Vin |A>o x a + t t > 1 (nsec) Inverter A is a CMOS inverter with effective output resistance of 1.5K. Vop = 2.5V and Vy = 07, Vr, = 18V. The input capacitance is 5 fF, Vpy was zero for <0, then a pulse generator (with very low output resis- tance) produces the input waveform shown above. (a) Sketch the general form of Vour(t) - / (b) Calculate Vour att = 0+,f = I nsec, and t = 2 nsec. (ce) Re-sketch Vour(+) very carefully and neatly. ve RC = (lSk+ 15k) (3p +10) 5 = » ouS5 Vot(o) = 2.5¢°%8 - 25 VatG) > 252 72 = -71GV -(2-1yY 2.547(:12-2.5)e% as G Wwt€2) 9 of 16 Solvtio “Sg lem. n: t (a) Vour A 4 > - rt t | —p | (nsec) 1 2 3 (b) Bb) Voyp(t 204) = 29 b.2) Voyp(t =I nsec) = __ 2» 72 b3) Voyp(t=2 nsec) = IA (c) Your B> ft (nsec) 10 of 16 évenin iv: i Find the Thévenin equivalent circuit for each of the following. a Ii, als A mK | Source. 4 om (a) | | trensformation av | Ve ° | | e 1K 2mA cae oe oo a Qu sis AmA 2K & 7G rposceroro a 36 | OclmA 2K » | | 1 Simp li cireatt } (b) ; phoma Ae eb RIN | 1K 2V | * Se 6 Co a Ve av | | A \ 2K KJ | Ue | : “@ 1 ae (©) |S2K 2K 3v I I< Ie Pv B | @) | Oe ue 2K B (Op-amps are ideal) bee ee 4 B (Op-amp is ideal) pots st tts rt sts teococc 4 | WW. | V+ =V- =O. IK 10K ~ I i€ A® spen “rch aa Ww Wy ; Va = Uo = ou | | | Nos apply tes ve ltecge } B So = Veltaag (tH Raw alwans ov lv 11 of 16 lem _ 7 Workshe oe 0.64 RC= 69% 3,5K * 192 10" ae C,, = ei Unit gate delay = _ 46¢ ps (b) (c) (d) e) ( Inverter A Inverter B Cie! es ee ioe RAKIGRY oe go" = a R, 37S) 21¢ R, S7s 2g OUC= :64v32,.5KK ALF a delay Unit gate delay a ea pS le {I3>0 |/5>0 GUC =.69 x BIS x¥S te delay Unit gate delay = Ot pS > AH, OGM C2 EX AUG XITZ EP delay ae : Unit gatedelay=__ ZY pS (f) Total of (c)+(@)+(@)_B! pS versus (a) U6Y¢ ps % daleys Se f deles | 14 of 16 s blem 8 lo: The layout of a CMOS logic circuit is shown below. Also shown on the page opposite is the cross-section E- E of the chip. The CMOS process is: (1) (2) (3) (4) (5) (6) (7) (8) (9) (dark field) ‘Oxide cut (dark field) Start: p-Type Si wafer Well mask, implant donors Grow field oxide 0.5um Polysilicon Contact & (clear field) (dark field) Pattern oxide (oxide cut for thin oxide) Grow gate oxide Deposit 0.5,1m polysilicon Pattern polysilicon Two select masks with implants (masks not shown) Deposit 0.5m oxide (10) Contact mask, etch oxide (11) Deposit 0.5,1m metal (12) Pattern metal (a) In the space provided, draw cross-section A-A. Use E-E as a guide for scale. (b) Draw cross-section B-B. Metal (clear field) (c) Label the inputs and outputs of this circuit on the figure above. (Note that there are 6 wires entering from the left and of these, only 2 are labeled, namely Vp and ground. You are to label the others and use these labels in part d.) (d) Write the logic function of the circuit (for example, OUT = (A +B) - C). 15 of 16 bles ns’ Silicon substrate Cross-section E. -- E. {a) Giicow- Qubskete | Cross-section A-A © (b) en ry [pyle See S103 si Wr Walls Siew | Subtiers. Cross-section B-B ({c) (Label figure on opposite page.) THe N AS TO PAvL PAR (d). Logic: Equation. 16 of 16 outs. Ar BC