A Gallery of Amplifier Circuits: Op-Amps and Differential Amplifiers, Study notes of Political Science

Download A Gallery of Amplifier Circuits: Op-Amps and Differential Amplifiers and more Study notes Political Science in PDF only on Docsity! 1 A Gallery of Amplifier Circuits ECE137A, March 2, 1995 The text is a good complement to the lecture notes, but has one major weakness: most of the circuits in the text are very simple, on a quite tutorial level. One can learn a lot by looking through a catalog of IC designs for various purposes, looking at the structure of real solid-state circuits. The old National Semiconductor Linear Applications Handbooks are great for this purpose, if you can find them (you might ask the electronics shop for a hint on this). In the same spirit, below are a bunch of circuits taken from ECE137A/B problem sets over the years. This is not an assignment, you dont need to work the problems...but the listing might be a good study guide for the final, and is certainly intended as a list of hints and tricks for the lab assignment. IC-like Operational Amplifiers The circuits in this section are true op-amps, having the following important parameters. High or very high DC voltage gain. High common-mode rejection ratio. Low or very low output impedance. Big maximum peak-peak output voltage swings, within 1- 2 volts of the power supply voltage. Operation over a wide range of DC power supply voltages with only moderate changes in circuit characteristics. It would be instructive to work out the voltage gain, CMRR, and maximum signal swing for these circuits Basic IC OP-AMP -Vee +Vcc -Vee 5ž 5ž 29 kž 42ž Cc In the op-amp circuit to the right, all NPN transistors have ß=100 and Va=100 Volts. All PNP devices have ß=50 and Va=75 Volts. Load resistance of ≈ 1000Ω, The power supplies are ±15 Volts. The compensation capacitor is quite important: see other notes. As in all high-gain amplifiers intended for use with negative feedback, bias analysis can be a little tricky. Work from assumption that the DC output voltage (bias condition) is zero volts: this is generally what the negative feeback network will force. 2 IC OP-AMP with Darlington Gain Stage -Vee 50k 280k 10ž 10ž 10ž50ž50ž Same transistor parameters as above. The darlington stage (e.g. the added emitter follower) increases the equivalent load impedance for the first (differential) stage, increasing its voltage gain. IC OP-AMP with Darlington Gain Stage and Darlington Output Stage 5 Differential Amplifiers These are not op-amps, being designed for use without negative feeback. In some cases, the circuits are quite high-performance in their own right; others are just "problem set" circuits included here to show various circuit tricks. AC-Coupled Low-Gain Differential Ampifier with Low output impedance Transistors: Q4 is 2N5089; Q8 is a 2N3906, and Q1,Q2 and Q3 are 2N5087. Assume all transistors are well-matched. The FET has Idss=10mA and Vp=-3 Volts. All bipolar transistors have Vbe(on)=0.7 V. This amplifier is a differential stage with a folded cascode and a buffer. The differential input is useful for DC coupling or for applications needing rejection of common-mode signals. The folded cascode (Q4) really has no impact on the voltage gain, but its level shifting greatly improves the amplifier's maximum peak-peak output swing. Q5 and Q6 are buffer stages providing a large current gain, so that low impeances can be driven. 6 101.1.01.001 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 2N5089 2N5087 Collector Current, mA C ur re nt G ai n Precision DC Coupled (Low-Gain) Differential Amplifier 750k -15 V 750k -15 V 200ž 200ž 1Mž1Mž -15 V 2.8kž 5.2kž 6 volt zener 2.2kž +15 V Vin- Vin+ 9 volt zener 4.3 kž 4.6 kž Vout 3 kž Q1 Q2 Q3 Q4 Q5 Q6 Q7 Transistors: Q1-Q5 are 2N5089; Q6 is 2N5087. Assume all transistors are well-matched. All transistors have Vbe(on)=0.65 V. VA=100 V(NPN), 80 V (PNP). Circuit design issues are quite similar to the previous amplifier. The differential stage in this case has very high input impedance. Q6, in the folded cascode configuration, provides level-shifting in order to improve the peak-peak drive capability, and Q7 is a buffer. The voltage gain is about 10 being approximately 4.6kΩ/(200Ω+200Ω+Re2+Re3). Can you see this without doing detailed circuit analysis? 7 High-Gain AC-Coupled Differential Amplifier 50ž 50ž 50ž 620ž Q2: 2n3904 6.8 V 1.6 kž 1.6 kž 5.6 kž +15 V -15 V NPD 5566 AD820 100ž100ž 360ž +15V 0.1 µF 7.5 kž 7.5 kž 0.01 µF 5.1 kž 50ž 2N3904 510 ž Rl=100ž MPSU55 (ß=150) 2N5462 0.1 µF 1 Mž 100ž0.1 µF 1 Mž 100ž 0.1 µF Vg1 Vg2 10 µF AD820 Matched pair: ß=75 NPD5566: Idss=15 mA, Vp=1.8 Volt, VA=100 V 2N5462: |Idss|=10 mA, |Vp|=4 volt, |VA|=80V All NPNs: Va=100 V; All PNPs: Va=80 V. Use the datasheet values for the 2N3904's. The 50Ω potentiometer is set so that the currents are balanced in the AD820 matched pair. This is a fairly high-gain differential amplifier. Use of cascaded differential pairs, combined with the constant current sources, leads to a very high common-mode rejection ratio.