Download Notes on Flip Flops, Registers and Register Files | CPSC 5155G and more Study notes Computer Architecture and Organization in PDF only on Docsity! Chapter 6 Flip–Flops, Registers, and Register Files A 4–Bit Register This uses four D flip–flops. When the LOAD signal is asserted, the register is loaded. Slide 1 of 14 slides CPSC 5155 Revised February 1, 2006 Chapter 6 Flip–Flops, Registers, and Register Files More on the LOAD Signal. All control signals are generated by a control unit, which interprets the machine language representing the program. When looking at components in isolation, we usually do not consider the source of the control signal, but assume it is generated validly. The control signal must be generated in time with the system clock. Slide 2 of 14 slides CPSC 5155 Revised February 1, 2006 Chapter 6 Flip–Flops, Registers, and Register Files Register Functionality A register controller should select from three functions (not two). 1) Do nothing – save the current contents 2) Copy the input to the register and possibly change its contents 3) Copy the register contents to the output. Also save the contents. This requires as least two control signals as 21 < 3 22. The previous example used Select and Load. Select Load Action 0 0 Do nothing 0 1 Do nothing 1 0 Copy data from register 1 1 Load data into register Slide 5 of 14 slides CPSC 5155 Revised February 1, 2006 Chapter 6 Flip–Flops, Registers, and Register Files Example of a Four General Purpose Register File Two-bit data buses and two-bit registers. Where is R0? Slide 6 of 14 slides CPSC 5155 Revised February 1, 2006 Chapter 6 Flip–Flops, Registers, and Register Files Loading the Registers Control signals are Bus Reg, Reg Bus, and the two–bit binary number R1R0, used to select the register. A Decoder generates the load signal for each register. NOTE:The decoder is enabled by the Bus Reg signal. If Bus Reg = 0, no register is loaded. There is no signal to load register 0 as there is no register 0. Slide 7 of 14 slides CPSC 5155 Revised February 1, 2006 Chapter 6 Flip–Flops, Registers, and Register Files How to Load a JK: Correct Version This also applies to SR flip–flops. If Load = 0, then J = 0 and K = 0 If Load = 1 then J = X and K = Not(X). Slide 10 of 14 slides CPSC 5155 Revised February 1, 2006 Chapter 6 Flip–Flops, Registers, and Register Files How Not to Load a JK: Mistake One The Load signal is asserted only when the register is to be loaded. Works OK if Load = 1. If Load = 1, then J = X and K = Not(X). If Load = 0, then J = 0 and K = 1. This is the “autoforget” memory. Slide 11 of 14 slides CPSC 5155 Revised February 1, 2006 Chapter 6 Flip–Flops, Registers, and Register Files How Not to Load a JK: Mistake Two Again, this works when Load = 1. If Load = 1, then J = X and K = Not(X). If Load = 0, then neither J nor K is defined. What happens depends on how the flip–flop is built. RULE: Don’t use tri–states on inputs. Slide 12 of 14 slides CPSC 5155 Revised February 1, 2006
