Notes on Pass Transistor Logic | ECEN 6263, Study notes of Electrical and Electronics Engineering

Download Notes on Pass Transistor Logic | ECEN 6263 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n High Speed Pipeline Implementation (Part 3) Pass Transistor Logic Pass transistor logic is slightly slower than domino logic because it must compromise between passing rising and falling edges quickly. Pass transistor logic is much easier to design than domino logic because carefully timed precharge clocks are not necessary. Pass transistor logic consumes less area and power than domino because high activity pre- charge clocks do not have to be distributed to each individual gate. Fig. 6.47(bottom), p. 346: Partial swing pass transistor logic (LEAP) is faster than full swing pass transistor logic (CMOSTG) because the reduced transistor count significantly reduces loading. Recall that the input voltage to the inverter without the keeper only reaches Vdd - VTn which is insufficient to completely turn off the pFET in the inverter and causes DC power consumption. A weak keeper is added as shown to eliminate the DC power consumption by pulling the inverter input voltage all the way to Vdd. The keeper must be weak because the pass nFETs must be able to overcome the keeper. The keeper increases delay by increasing the load on the inverter input and output. The keepers can be eliminated on critical delay paths to reduce worst case delay at the expense of additional power. Keepers should always be used on non-critical delay paths to reduce power consumption.High Speed Pipeline Implementation (Part 3) December 5, 2006 page 1 of 6 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n Recall also that the rise time of the nFET pass transistors is slow because the nFETs are not good at passing 1’s. The average delay can be reduced by using low skew (low Vinv, big nFET, small pFET) inverters. A low skew inverter can respond much more quickly than a high skew inverter to a slow rising edge. The difference in response to a fast falling edge is small. A low skew inverter with Z = Wp/Wn = 1 is usually a good choice since Vinv < Vdd/2 because of the higher pFET channel sheet resistance. Fig. 6.47(middle), p. 346: Dual rail partial swing pass transistor logic (CPL). Dual rail with keeper is faster than single rail with keeper because the dual rail keeper is turned on earlier than the single rail keeper. The single rail keeper is turned on after an inverter delay and the dual rail keeper is turned on directly by the fast falling edge out of the pass nFETs. Design Example Fig. 10.17a, p. 651 and eq. 10.4, p. 646: Building block for the valency-2 tree adders. HnFETs X L VX t tdrH tdrL tdfH tdfL VinvH VinvL VX VX t without keepers with keepers single rail dual railHigh Speed Pipeline Implementation (Part 3) December 5, 2006 page 2 of 6 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n Faster to have a separate Pi:k and Pi:k gate at each level. Then Pi:k, Pi:k and Gi:k all have about same delay. A dual rail implementation for Pi:k and Pi:k is combined with the Gi:k gate. Pi:j Pk-1:j Pi:k Pi:k Pk-1:j Pi:j Pi:k Pi:k odd levels even levels Pi:j Pk-1:j Gi:j Gk-1:j Gi:k Gi:j Pi:j Gk-1:j Gi:kHigh Speed Pipeline Implementation (Part 3) December 5, 2006 page 5 of 6 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n Static CMOS. Gk-1:j Pi:k Gi:k Gi:j Pk-1:j Pi:k Pi:j Gi:k Pi:kGk-1:j Pi:kPk-1:j odd levels Gk-1:j Pi:k Gi:k Gi:j Gi:k Pi:k Gk-1:j Pk-1:j Pi:k Pi:j Pi:k Pk-1:j even levelsHigh Speed Pipeline Implementation (Part 3) December 5, 2006 page 6 of 6