Lab Report: Implementing 4-bit Ripple Carry Adder with VHDL - Prof. Gregory W. Donohoe, Lab Reports of Electrical and Electronics Engineering

Download Lab Report: Implementing 4-bit Ripple Carry Adder with VHDL - Prof. Gregory W. Donohoe and more Lab Reports Electrical and Electronics Engineering in PDF only on Docsity! ECE 241 Lab 7– Iterative Circuits: Ripple Carry Adder  Objective Implement a 4-bit unsigned adder as an iterative circuit, using structural VHDL. of Harris & Harris) • Understand the principle of iterative circuits and the ripple carry adder (See Harris & Harris, p. 52 and p. 234). • Understand the concept of structural VHDL to represent the logical structure of a design (See Harris & Harris, Section 4.3) • Implement a design with multiple modules and multiple VHDL source files • Connect std_logic and std_logic_vector signal elements in a design. Prelab (5 pts) Bring in a sketch of your design (a schematic or block diagram) and a draft of your VHDL code. Know how to instantiate a component in VHDL. Experiment (10 pts) Create two VHDL source files: 1. A full adder (FA), with inputs A, B, and Cin, and outputs S and Cout, of type std_logic. 2. A 4-bit ripple-carry adder that instantiates four copies of your full adder. The inputs to the 4-bit adder are A and B, of type std_logic_vector, and Cin, of type std_logic. Outputs are S, of type std_logic_vector, and Cout, of type std_logic. Create a testbench and perform behavioral simulation of your full adder. Create a testbench and perform behavioral simulation of our 4-bit adder. Find a set of inputs that will stimulate the critical path, i.e., that will take the longest amount of time to complete. Implement the design and download it to the Digilent board. Use: - 4 slide switches for 4-bit input A - 4 slide switches for 4-bit input B - 1 momentary pushbutton for Cin - Use your imagination to find a way to represent Cout Report (5pts) Turn in a brief, professional report that describes your design process and results. Comment on the “efficiency” of VHDL coding styles, e.g., dataflow versus structural, and any problems you encountered. Finally, attach to your report hardcopies of your VHDL, post-route simulation, and the signed design summary. Don’t forget conclusions!