Notes on Register File Design | Advanced VLSI Design and Applications | ECEN 6263, Study notes of Electrical and Electronics Engineering

Download Notes on Register File Design | Advanced VLSI Design and Applications | ECEN 6263 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n Register File Design Register files are an important component for implementing registers in modern computer design. The heart of the computer processor is the number crunching or processing units. We have already covered the basic design of these types of components. The processing units must be connected to the internal storage registers as shown. Note that the internal registers are different than main memory in that many different busses connect to the reg- isters but usually only one bus connects to memory elements. This greatly reduces the cost of memory elements, but makes them unsuitable for direct connection to the process- ing units. multi- plier Registers logic unit Barrel shifter Adderfloating point unit vector unit Memory Units The diagram clearly shows that there is a data flow bottleneck (the Von Neuman bottle- neck) between the registers and memory. The computer processor operates much more efficiently when there are enough registers so that only occasionally does data need to be transferred between registers and memory. Typically dozens or even hundreds of registers are desirable. The interconnect area will be much too large if it is necessary to directly connect each individual register to each processing unit. This is why processor registers are usually implemented as register files. Register files are like memory in that only a lim- ited number of connections (ports) are provided to each register and the same connections are shared by different registers. Register files are unlike memory in that many more con- nections (ports) are provided than is typical for ordinary memory. Implementation of Data Storage Element The most obvious choice for implementation of a bit of data storage in the register file is the clocked D-FF. However, routing clock signals to the extremely large number of bits (104 to 105) in the register file takes up too much area. Asynchronous storage elements take up much less space because they do not require clock signals. Storage cells from ordinary memory designs can be adapted for use in the register file by providing interfaces to more than one address and data bus, i.e. a multi-port memory.Register File Design October 24, 2006 page 1 of 4 E C E N 6 2 6 3 A d v a n c e d V L S I D e s i g n The smallest memory cell is the dynamic RAM cell. The dynamic RAM cell is usually not used for register files for the following reasons. 1. Dynamic RAM has additional overhead circuitry for refresh. Even though the register file is large, it still is a very small memory and the size (expense) of the overhead may be too large. Also, there is no time available to insert extra refresh cycles since the reg- ister file is used every clock cycle. 2. Dynamic RAM is relatively slow compared with other memory cells. This is because the storage cell capacitance in dynamic RAM must be made as large as possible in order to produce a significant change on the bit lines. Unfortunately, the settling time of the bit lines increases as the storage capacitance increases. 3. Dynamic RAM is normally implemented in specialized fabrication processes that have been optimized particularly for dynamic RAM. It may be difficult to get dynamic RAM to work well in fabrication processes used for ordinary digital integrated circuits. For these reasons, a static RAM cell is usually used in register files. Recall from our dis- cussion of memory design earlier that each static RAM cell requires a bit and bit line to be able to write new data in the cell. With the standard static RAM cell, it is possible either to read two data simultaneously (the bit and bit line can be used to read different data) or write one datum ((the bit and bit line must have the same datum). Each of the processing units usually requires an interface to the registers that can quickly read 2 input operands (source operands) and write 1 output operand (destination operand). If pipelining is done so that simultaneous reads and writes are not necessary, then a register file based on the static RAM cell with 2 single ended reads or 1 double ended write is adequate for inter- facing to a single processing unit. More advanced computer processor design requires that several processing units should be connected to the same register file. One approach has been to partition the register file into pieces that are dedicated to each hardware unit. For example, the floating point unit often has a special set of registers. The problem is that many machine instructions and much time must be wasted in moving the data between registers. The true advantages of advanced processor design are achieved more effectively when many input and output ports are provided to each individual register in the register file so that many of the hard- ware units can use the several registers simultaneously. The simplest thing to do is to add additional pairs of bit lines as in a normal multiport RAM. Fortunately, if we use single ended reads, then we have an additional 2 reads or 1 write for each pair of added bit lines which is exactly what is needed for interfacing to each added processing unit. As an example design, consider a register file cell with 3 pairs of bit lines. This type of register file is usually operated so that reads on all busses are done at the same time and writes are done at the same time, never a mixture of reads and writes. This design allows 6 simultaneous single ended reads by putting different addresses on the 6 address busses, A1, B1, A2, B2, A3, B3. Also, 3 simultaneous double ended writes are allowed by putting different addresses on the 3 pairs of address busses, (A1,B1), (A2,B2), (A3,B3). Register File Design October 24, 2006 page 2 of 4