Analysis and Design of Sequential Circuits: Flip-Flops and Sequence Detection - Prof. Edwa, Study notes of Computer Architecture and Organization

Download Analysis and Design of Sequential Circuits: Flip-Flops and Sequence Detection - Prof. Edwa and more Study notes Computer Architecture and Organization in PDF only on Docsity! Sequential Circuits We have spent some time considering combinational circuits. We now consider sequential circuits; that is, circuits with memory. Feedback is one specific type of memory. By feedback we mean applying the output of a circuit back to its input. We compare the two types of circuits. Combinational Circuits Sequential Circuits No Memory Memory No flip-flops, Flip-flops may be used only combinational gates Combinational gates may be used No feedback Feedback is allowed Output for a given set of The order of input change Inputs is independent of is quite important and may order in which these inputs produce significant differences were changed, after the in the output. output stabilizes. The following figure shows a way to consider sequential circuits. The input is fed into the combinational logic (AND gates, OR gates, and NOT gates). The output of the combinational logic is fed into the memory and available as input to the combinational logic on the next tick of the clock. The clock input is very important to the concept of a sequential circuit. At each “tick” of the clock the output of a sequential circuit is determined by its input and by its state. By Q(T) we denote the state of a sequential circuit at time T – this is basically its memory. We watch the state of the circuit change from Q(T) to Q(T + 1) as the clock ticks. We have two topics about sequential circuits to be covered in this section: 1) Analysis of sequential circuits 2) Design (synthesis) of sequential circuits Circuit analysis begins with a circuit diagram or a black box and ends with an identification of the sequential circuit implemented by the device – normally a truth table. The steps are: 1) Identify the inputs and the outputs 2) Express each output as a Boolean function of the inputs and the present state Q(T) 3) Identify the circuit if possible. Circuit design begins with a complete description of the circuit and ends with a design. There are two types of sequential circuits – synchronous and asynchronous. Asynchronous circuits do not have a common clock; they are faster and harder to design. As should be inferred from the previous discussion we shall focus on synchronous circuits. The basic building blocks of synchronous circuits are flip-flops, which should be considered as single bit memory elements: each flip-flop can store either a 0 or a 1. Flip-flops have inputs, outputs, and state Q(T); Q(T) = 0 or Q(T) = 1. The outputs of a flip-flop at any given time are the present state and its complement: Q(T) and Q’(T). There are two standard ways to describe a flip-flop: the characteristic table and the excitation table. A characteristic table is a truth table that determines the next state of the flip-flop in terms of the input and present state. An excitation table specifies the input required to produce a desired next state at Q(T + 1) given the present state at Q(T). There are four basic types of flip-flops: SR, JK, D, and T. We shall specify each flip-flop by the characteristic and excitation tables and ignore the details of its construction. The SR flip-flop has two inputs S and R. The clock input is always present and shown here just to be complete. We first give the characteristic table as a truth table. S R Q(T + 1) 0 0 Q(T) 0 1 0 1 0 1 1 1 Not allowed – error The excitation table for the flip-flop is shown at Q(T) Q(T + 1) S R the right. Note that the table shows what 0 0 0 d inputs are required to get the desired next 0 1 1 0 state given the existing present state. 1 0 0 1 NOTE: We have some new terminology 1 1 d 0 to explain. Q Q’ S R Clock We use the following variables in the analysis of this circuit with a single flip-flop. X denotes the input, Y denotes the output of the flip-flop (Y’ also), and Z the output of the circuit. The first step is to determine the equations for Z, the output, and D, the input to the flip-flop. By inspection, we determine the following for the equations: Z = X  Y’ + X’  Y D = X + Y Noting that Q = Y (the state of a flip-flop is also its output) we construct the following Next- State diagram for the flip-flop, based on the characteristic table of a D flip-flop. X Q(T) D Q(T + 1) 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 The output table is similarly constructed X Q(T) Z 0 0 0 0 1 1 1 0 1 1 1 0 These two tables are combined to form the transition table. X Q(T) Q(T + 1) / Z 0 0 0 / 0 0 1 1 / 1 1 0 1 / 1 1 1 1 / 0 The final step in the process may be the creation of the state diagram. At this point, we have a complete description of the circuit. It may be possible to proceed from this diagram to obtain an understanding of what the circuit does. This circuit is a 2-state device, with memory represented by one bit. The circuit stays in state 0 from the start until a 1 is input at which time it transitions to state 1 and remains there. Note the relation of the output to the input, depending on the state of the machine. Input Q(T) Output 0 0 0 For Q(T) = 0, the output is X 1 0 1 0 1 1 For Q(T) = 1, the output is X’. 1 1 0 A verbal description of the circuit is then that it copies its input to the output until the first 1 is encountered in the input stream. After that event, all input is output as complemented. What this circuit does is take the two’s-complement of a binary integer, presented to the circuit least-significant bit first. It is easy to prove that such a strategy produces the two’s complement of a number. First, consider a number ending in 1, say XnXn-1…. X2X11. The one’s complement of this number is Xn’Xn-1’ …. X2’X1’0. Adding 1 to this produces the number Xn’Xn-1’ …. X2’X1’1, in which the least significant 1 is copied and the remaining bits are complemented. The proof is completed by supposing that the number terminates in a one or more zeroes; i.e., its least significant bits are 10 …. 0, where the count of zeroes is not important. The one’s-complement of this number will end with 01 …. 1, where each zero in the original has turned to a 1. But 01 …. 1 + 1 = 10 …. 0, and up to the least significant 1 the two’s-complement is a copy of the bits in the integer itself. Note that there is no carry out of the addition that produced the right-most 1, so the remainder of the integer is formed by the one’s-complement. Thus we have a complete description of the circuit. It is a serial two’s-complementer. Design of Sequential Circuits Having seen how to analyze digital circuits, we now investigate how to design digital circuits. We assume that we are given a complete and unambiguous description of the circuit to be designed as a starting point. At this level, most design problems focus on one of two topics: modulo-N counters and sequence detectors. A sequence detector accepts as input a string of bits: either 0 or 1. Its output goes to 1 when a target sequence has been detected. There are two basic types: overlap and non-overlap. In an sequence detector that allows overlap, the final bits of one sequence can be the start of another sequence. Our example will be a 11011 sequence detector. It raises an output of 1 when the last 5 binary bits received are 11011. At this point, a detector with overlap will allow the last two 1 bits to serve at the first of a next sequence. By example we show the difference between the two detectors. Suppose an input string 11011011011. 11011 detector with overlap X 11011011011 Z 00001001001 11011 detector with no overlap Z 00001000001 The sequence detector with no overlap allowed resets itself to the start state when the sequence has been detected. Write the input sequence as 11011 011011. After the initial sequence 11011 has been detected, the detector with no overlap resets and starts searching for the initial 1 of the next sequence. The detector with overlap allowed begins with the final 11 of the previous sequence as ready to be applied as the first 11 of the next sequence; the next bit it is looking for is the 0. Here is an overview of the design procedure for a sequential circuit. 1) Derive the state diagram and state table for the circuit. 2) Count the number of states in the state diagram (call it N) and calculate the number of flip-flops needed (call it P) by solving the equation 2P-1 < N  2P. This is best solved by guessing the value of P. 3) Assign a unique P-bit binary number (state vector) to each state. Often, the first state = 0, the next state = 1, etc. 4) Derive the state transition table and the output table. 5) Separate the state transition table into P tables, one for each flip-flop. WARNING: Things can get messy here; neatness counts. 6) Decide on the types of flip-flops to use. When in doubt, use all JK’s. 7) Derive the input table for each flip-flop using the excitation tables for the type. 8) Derive the input equations for each flip-flop based as functions of the input and current state of all flip-flops. 9) Summarize the equations by writing them in one place. 10) Draw the circuit diagram. Most homework assignments will not go this far, as the circuit diagrams are hard to draw neatly. We now do the 11011 sequence detector as an example. We shall break some of the above big steps into sub-steps to make things easier. We begin with the formal problem statement. Step 2 – Determine the Number of Flip-Flops Required We have 5 states, so N = 5. We solve the equation 2P-1 < 5  2P by inspection, noting that it is solved by P = 3. So we need three flip-flops. Step 3 – Assign a unique P-bit binary number (state vector) to each state. The simplest way is to make the following assignments A = 000 B = 001 C = 010 D = 011 E = 100 Occasionally, a better assignment can be detected by inspection of the next state table. I note that the next states in the table cluster into two disjoint sets for X = 0 and X = 1. For X = 0 the possible next states are A and D For X = 1 the possible next states are B, C, and E. For this reason, I elect to give even number assignments to states A and D, and to give odd number assignments to states B, C, and E. Being somewhat traditional, I want to assign the state numbers in increasing order so that we don’t get totally confused. The assignment is A = 000 B = 001 C = 011 Note that states 010, 110, and 111 are not used. D = 100 E = 101 Step 4 – Generate the Transition Table With Output Note that in many designs, such as counters, the states are already labeled with binary numbers, so the state table is the transition table. We shall label the internal state by the three bit binary number Y2Y1Y0 and use the three-bit vectors defined above. Present State Next State / Output X = 0 X = 1 Y2Y1Y0 Y2Y1Y0 / Z Y2Y1Y0 / Z A 0 0 0 0 0 0 / 0 0 0 1 / 0 B 0 0 1 0 0 0 / 0 0 1 1 / 0 C 0 1 1 1 0 0 / 0 0 1 1 / 0 D 1 0 0 0 0 0 / 0 1 0 1 / 0 E 1 0 1 0 0 0 / 0 0 1 1 / 1 Step 4a – Generate the Output Table and Equation The output table is generated by copying from the table just completed. The output equation can be obtained from inspection. As is the case with most sequence detectors, the output Z is 1 for only one combination of present state and input. Thus we get Z = X  Y2  Y1’  Y0. This can be simplified by noting that the state 111 does not occur, so the answer is Z = X  Y2  Y0. Step 5 – Separate the Transition Table into Three Tables, One for Each Flip-Flop We shall generate a present state / next state table for each of the three flip-flops; labeled Y2, Y1, and Y0. It is important to note that each of the tables must include the complete present state, labeled by the three bit vector Y2Y1Y0. Y2 Y1 Y0 PS Next State PS Next State PS Next State Y2Y1Y0 X = 0 X = 1 Y2Y1Y0 X = 0 X = 1 Y2Y1Y0 X = 0 X = 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 Match Y1 Y2Y0’ 0 Y0 0 1 Before trying step 6, I shall note a quick, but often messy, implementation. We look at an implementation using D flip-flops only. For each flip-flop, we have the desired next state for each combination of present state and input. Remember that the D flip-flop equation is D = Q(T + 1); i.e., input to the flip-flop whatever the next state is to be. Thus, this design is D2 = X’Y1 + XY2Y0’ D1 = X Y0 D0 = X While this may be an acceptable implementation, it is important to complete the original design problem using JK flip-flops. What we want is input equations for J2, K2, J1, K1, J0, and K0. Inspection of the above gives little clue for the first two flip-flops, but any student recalling the use of a JK flip-flop to implement a D flip-flop will see immediately that the input equation for flip-flop 0 is J0 = X and K0 = X’. Step 6 – Decide on the type of flip-flops to be used. The problem stipulates JK flip-flops, so we use them. As an aside, we examine the difficulties of designing the circuit with D flip-flops. Present State X = 0 X = 1 Y2Y1Y0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 1 Step 7 – Derive an Input Table for Each Flip-Flop using its Excitation Table and Step 8 – Produce the Input Equations for Each Flip-Flop It is at this point that we first use the fact that we have specified JK flip-flops for the design. We have already considered a D flip-flop implementation. Because we are using JK flip- flops, we show the excitation table for a JK flip-flop. Q(T) Q(T + 1) J K 0 0 0 d We shall see shortly how the presence of the 0 1 1 d d (Don’t Care) state simplifies design. 1 0 d 1 1 1 d 0 It is at this point that neatness counts. For each flip-flop we shall write out the complete present state and the next state of the specific flip-flop. We then use the present state and next state of the specific flip-flop to determine its required input. The problem here is comparing the next state of the flip-flop to the correct present state. First we do Y2. Probably the easiest way to generate this table is to do all of the “0 to 0” transitions first, then the “0 to 1”, etc. For this flip-flop, be sure to refer back to the Y2 part of the PS. We now try to produce the input equations for J2 and K2 by simplifying the above columns. The best way is to consider first the X = 0 columns, then the X = 1 columns and finally to combine the two. There are formal ways to do this, but I try simple matching. 1) If a column has only 0 and d, it is matched by 0. 2) If a column has only 1 and d, it is matched by 1. 3) If this does not work, try a match to one of Y2, Y1, or Y0. Remember, the d entries do not have to match anything. Consider X = 0. In the above, for J2, we have only 001 as a real pattern. These copy the pattern seen in Y1, so we make the assignment that for X = 0, J2 = Y1. For X = 0, the only pattern seen is a pair of 1’s, so for X = 0 we set K2 = 0. X = 0 X = 1 J2 = Y1 J2 = 0 thus, J2 = X’Y1 K2 = 1 K2 = Y0 thus, K2 = X’ + XY0 = X’ + Y0. Note the combination rule X’(expression for X= 0) + X(expression for X = 1). Applied to J2, the rule gives J2 = X’Y1 + X0 = X’Y1 The second simplification uses the absorption law: X’ + XY = X’ + Y for any X and Y. Y2Y1Y0 X = 0 X = 1 Y2 J2 K2 Y2 J2 K2 0 0 0 0 0 d 0 0 d 0 0 1 0 0 d 0 0 d 0 1 1 1 1 d 0 0 d 1 0 0 0 d 1 1 d 0 1 0 1 0 d 1 0 d 1 More on the Combination Rule Some students have trouble with the combination rule. I quote it again, give an example and then give a theoretical underpinning for it. The rule for combining expressions derived separately for X = 0 and X = 1 is X’(expression for X= 0) + Xexpression for X= 0) + X(expression for X= 0) + Xexpression for X = 1). The origin of the combination rule is the following observation. Consider the Boolean expression J = X’A + XB, where A and B are any Boolean expressions. When X = 0, this becomes J = 1A + 0B = A, and when X = 1, this becomes J = 0A + 1B = B. We then see that J = X’A + XB if and only if J = A when X = 0 and J = B when X = 1. This simple observation is the source of the combination rule. It will always produce a correct result and usually produce the simplest result. Suppose we had derived the following patterns for K2 in a problem with three flip-flops. When X = 0, K2 = 1, and when X = 1, K2 = Y0 The result of the combination law is that K2 = X’1 + XY0 = X’ + XY0. We shall show in a moment that this expression can be simplified to K2 = X’ + Y0. The simplest expression obtainable is when the results from the two sides X = 0 and X = 1 are the same. Then we have the expression X’A + XA = (X’ + X)A = A. Two other cases: A = 0 J = XB B = 0 J = X’A The Absorption Theorem (T4a on page 22) can lead to simplifications that are useful. This occurs when either A = 1 or B = 1. Thus we can have the two following variants: S1 J = X’ + XB simplifies to J = X’ + B S2 J = X’A + X simplifies to J = A + X We provide proofs for both of these claims. S1 X’ + XB = X’ + B If X = 0, we have 0’ + 0B = 0’ + B, or 1 = 1 + B, which is true. If X = 1, we have 1’ + 1B = 1’ + B, or 0 + 1B = 0 + B, which is true. S2 X’A + X = A + X If X = 0, we have 0’A + 0 = A + 0, or 1A + 0 = A, which is true, If X = 1, we have 1’A + 1 = A + 1, or 1 = A + 1, which is true. Using the first of these theorems, we find that K2 = X’1 + XY0 = X’ + XY0= X’ + Y0. It may be possible to produce a counterexample to the claim that the combination rule produces the simplest result, but this author is not able to construct one. More on Overlap – What it is and What it is not At this point, we need to focus more precisely on the idea of overlap in a sequence detector. For an extended example here, we shall use a 1011 sequence detector. The next figure shows a partial state diagram for the sequence detector. The final transitions from state D are not specified; this is intentional. Here we focus on state C and the X=0 transition coming out of state D. By definition of the system states, State C – the last two bits were 10 State D – the last three bits were 101. If the system is in state D and gets a 0 then the last four bits were 1010, not the desired sequence. If the last four bits were 1010, the last two were 10 – go to state C. The design must reuse as many bits as possible. Note that this decision to go to state C when given a 0 is state D is totally independent of whether or not we are allowing overlap. The question of overlap concerns what to do when the sequence is detected, not what to do when we have input that breaks the sequence. Just to be complete, we give the state diagrams for the two implementations of the sequence detector – one allowing overlap and one not allowing overlap. The student should note that the decision on overlap does not affect designs for handling partial results – only what to do when the final 1 in the sequence 1011 is detected. A Word About Counters and Numbering their States For this example, we consider modulo-4 counters, both up-counters and down-counters. Modulo-4 up-counters count 0, 1, 2, 3, 0, 1, 2, 3, 0, etc. Modulo-4 down-counters count 0, 3, 2, 1, 0, 3, 2, 1, 0, etc. Sequence detectors, such as that just studied, have input – specifically representing the stream of bits to be detected. Pure counters do not have input; specifically neither an up-counter nor a down-counter has input. An up-down counter does have a single input, denoted as X, indicating the direction in which to count. Here are the state diagram and state table of a modulo-4 down counter. The state table shows the present state and next state. PS NS PS = Present State 0 3 NS = Next State 1 0 2 1 3 2 In this, and all counters the association of state vectors to the states is forced: 0 = 00, 1 = 01, 2 = 10, 3 = 11. Any other assignment yields a different counter. Here are the state diagram and state table of a modulo-4 up-down counter Here, the state table depends on X – the input used to specify the counting direction. PS Next State X = 0 X = 1 0 1 3 1 2 0 2 3 1 3 0 2 Again, the assignment of binary numbers follows a fixed and specific pattern. BOTTOM LINE: In a counter, states are named by the number they represent. In any modulo-4 counter, the states are named 0, 1, 2, and 3. The assignment of binary numbers or vectors to the states must follow a fixed rule – give the state a binary number corresponding to its representation as an unsigned binary number. For a modulo-4 counter, these assignments must be as follows: 0 = 00 1 = 01 2 = 10 3 = 11. Any other assignment yields a different counter design. If we wanted to provide extra fault tolerance, we would demand that when one light is either green or yellow, the other must be red, thus generating the equations R1 = (G1 + Y1)’ + G2 + Y2 and R2 = (G2 + Y2)’ + G1 + Y1 A bit of reflection will show that, even with this design, it is possible for one light to show more than one color. Here we assume a person seeing both red and green on a traffic light would assume something is very wrong. We now consider the state transition table expressed in terms of Q2, Q1, and Q0. Before breaking this into three tables, one for each flip-flop, we note the handling of the supposedly non-reachable states 6 and 7. The design here is based on fault tolerance, the idea that the circuit should have some ability to restore itself from faulty operation. Admittedly, the strategy reflected in this design may not be realistic. It is shown mostly to draw the student’s attention to the concepts and not to present an optimal solution. Step 5: Separate the Table into Three Tables, One for Each Flip-Flop Remember that each table must have a complete description of the present state. Q2 Q1 Q0 PS NS PS NS PS NS Q2Q1Q0 Q2 Q2Q1Q0 Q1 Q2Q1Q0 Q0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 Present State Next State Q2Q1Q0 Q2Q1Q0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 2 0 1 0 0 1 1 3 0 1 1 1 0 0 4 1 0 0 1 0 1 5 1 0 1 0 0 0 6 1 1 0 0 0 0 7 1 1 1 0 0 0 Step 6 – Select the Flip-Flop Type and Copy Its Excitation Table Since the JK flip-flops seem to be the Q(T) Q(T + 1) J K most useful type, I have selected to 0 0 0 d use JK’s in the design. As a reminder 0 1 1 d I have written the excitation table for 1 0 d 1 this flip-flop to the right. 1 1 d 0 Step 7 – Derive the Input Table for Each Flip-Flop Flip-Flop 2 Flip-Flop 1 Flip-Flop 0 PS NS Input PS NS Input PS NS Input Q2Q1Q0 Q2 J2 K2 Q2Q1Q0 Q1 J1 K1 Q2Q1Q0 Q0 J0 K0 0 0 0 0 0 d 0 0 0 0 0 d 0 0 0 1 1 d 0 0 1 0 0 d 0 0 1 1 1 d 0 0 1 0 d 1 0 1 0 0 0 d 0 1 0 1 d 0 0 1 0 1 1 d 0 1 1 1 1 d 0 1 1 0 d 1 0 1 1 0 d 1 1 0 0 1 d 0 1 0 0 0 0 d 1 0 0 1 1 d 1 0 1 0 d 1 1 0 1 0 0 d 1 0 1 0 d 1 1 1 0 0 d 1 1 1 0 0 d 1 1 1 0 0 0 d 1 1 1 0 d 1 1 1 1 0 d 1 1 1 1 0 d 1 Step 8 – Derive the Input Equation for Each Flip-Flop J2 = Q1  Q0 J1 = Q2’  Q0 J0 = Q2’ + Q1’ K2 = Q1 + Q0 K1 = Q2 + Q0 K0 = 1 Step 9 – Summarize the Equations Not needed – there are no other equations. Step 10 – Draw the Circuit The circuit is shown on the next page of the notes. The diagram has three parts. 1) The middle part is the design from steps 8 and 9 of the above work. It shows the design of what is essentially a modulo-6 counter. 2) The top part contains the circuits that implement the equations for R1, Y1, G1, etc. as found in the first part of step 4 of the design. This is essentially the output of the circuit – six signals that control six traffic lights. 3) The bottom part of the circuit is what provides clock pulses to the modulo-6 counter. Note that the circuit is a shift register used to provide a clock pulse at irregular intervals: at T = 1, T = 6, and T = 8, providing for unequal length of light phases. In this design, the input CLOCK is a regular signal, say one tick per second. The shift register at the bottom of the diagram shifts a single 1 around in a circular pattern, causing an output at T = 1, T = 6, and T = 8 (or 0). It is this irregular output that causes the modulo-6 counter in the middle of the diagram to move to the next state. We postulate that the circuit begins in state 0 (RR) and moves as follows. State Alias Duration Ends at 0 RR 1 T = 1 1 RG 5 T = 6 2 RY 2 T = 8 (T = 0) 3 RR 1 T = 1 4 GR 5 T = 6 5 YR 3 T = 8 (T = 0) We now consider the idea of a “register box” (this author’s terminology). This is a collection of a number of registers, generally a power of 2, each containing the same number of bits. Suppose N = 2K registers, each holding M bits. The register box has M input lines, labeled IN(M - 1) - 0 M output lines, labeled OUT(M - 1) - 0 K register select lines, labeled R(K – 1) – 0 Load, Select, and Clock signals For example, consider a set of 16 registers, each 32-bit. Since 24 = 16, we would represent the collection of registers by the following diagram, which hides all of the details. This idea of a register box is introduced in order to simplify the logic diagrams and focus on the high-level aspects of the computer architecture. To draw the diagram at left with basic flip-flops would require 32 flip-flops for each of the 16 registers or 16  32 = 512 flip-flops in all. In order to complete this design, we need to mention one feature of commercial decoders that we have ignored up to this moment – the enable input. Most decoders are enabled low, but we shall consider an enabled-high 3-to-8 decoder as an example. In this diagram, when Enable = 0, all outputs are set to 0, without reference to the input R2, R1, and R0. When enable = 1, the selected output is set to 1 and the others to 0. For example, if Enable = 1, R2 = 0, R1 = 0, and R0 = 0, then Output 0 is set to 1 and the others set to 0. The application to the above register box can be clearly seen. The Select input to the register box is connected to the Enable input of a decoder used to select the register. If Select = 0, then the decoder is not enabled and no register is active. If Select = 1, then the decoder is enabled and the selected register is active. An alternate design, used in this textbook, is to disallow register 0 so that no register is selected and active when all register select inputs are 0. Registers: Some Miscellaneous Remarks We now consider a few designs for registers to be constructed from flip-flops. Since the issues to be considered do not depend on the number of bits to be stored in the register, we consider a 1-bit register. Consider the following design. The input to this circuit is X. When Load = 1, the output of the AND gate is X and the input to the flip-flop is J = X and K = X’, as desired. The problem arises when the register is to keep its contents and Load = 0. The output of the AND gate is 0 and the input to the flip-flop is J = 0 and K = 1. The flip-flop is cleared; the auto-forget option. The correct circuit is shown at the right. When Load = 1, the input to the flip-flop is J = X and K = X’, as desired. When Load = 0, the input to the flip-flop is J = 0 and K = 0, and the flip-flop maintains its current state. We now consider the use of tri-state buffers to control input. When Load = 1, the circuit operates as desired. But consider Load = 0. Both tri-states are disabled, giving a high-impedance output, which is interpreted as logic 1 by the flip-flop. When Load = 0, we have J = 1 and K = 1 and that is trouble. The bottom line: tri-states cannot be used on input. Shift Registers We now consider the following circuit built from four D flip-flops. Before each clock pulse, D3 = X and DK = QK+1 for 0  K  2. If QK(T) is the state before the clock pulse and QK(T + 1) is the state after the clock pulse, then the situation after the clock pulse is given by Q3(T + 1) = X and QK(T + 1) = QK+1(T) for 0  K  2. The input bits in X are thus seen to be shifted across the four flip-flops, hence the name. Since we don’t like to draw too many flip-flops, we have a symbol for shift registers. The shift register has both serial input and parallel input. The parallel input is through the lines labeled by the Y’s, a notation we have normally used for output only. Two common modes are parallel in / serial out and serial in / parallel out. Shift registers are of great use for handling serial Input/Output devices, which transmit data one bit at a time. Consider the case of a character ‘B’ coming in on a serial input line. The ASCII character code for ‘B’ is 42 hexadecimal, so the binary input is 01000010. This input is passed into an 8-bit shift register. After 8 clock cycles, the state of the shift register is Y7 = 0, Y6 = 1, Y5 = 0, Y4 = 0, Y3 = 0, Y2 = 0, Y1 = 1, and Y0 = 0. This is then transferred into the CPU as parallel data. For output, the character code is transferred in parallel into the shift register and then shifted out one bit at a time, producing the serial bit stream. More detailed study of serial I/O indicates that there are a few more details to be considered.