DC-DC Converter Control Method and Circuit with Minimum Pulse Width Setting and Detection, Summaries of Electrical Engineering

Download DC-DC Converter Control Method and Circuit with Minimum Pulse Width Setting and Detection and more Summaries Electrical Engineering in PDF only on Docsity! (19) United States US 20120268.093A1 (12) Patent Application Publication (10) Pub. No.: US 2012/0268093 A1 YAMADA (43) Pub. Date: Oct. 25, 2012 (54) DC-DC CONVERTER CONTROL METHOD AND DC-DC CONVERTER CONTROL CIRCUIT (75) Inventor: Kouhei YAMADA, Matsumoto-city (JP) (73) Assignee: FUJI ELECTRIC CO.,LTD., Kawasaki-shi (JP) (21) Appl. No.: 13/455,530 (22) Filed: Apr. 25, 2012 (30) Foreign Application Priority Data Apr. 25, 2011 (JP) ................................. 2011-097453 110 120 124 121 Publication Classification (51) Int. Cl. GOSF I/56 (2006.01) HO3K 7/08 (2006.01) (52) U.S. Cl. ......................................... 323/283; 327/291 (57) ABSTRACT The transient response of an output Voltage to a load fluctua tion is improved, in a Switching power source that carries out a PWM control. In a DC-DC converter wherein a switching element of an output stage is controlled by a drive signal, whose pulse width is set at a minimum value, output from a PWM signal generating circuit based on an output Voltage output from an error amplifier in accordance with the differ ence between a feedback Voltage in accordance with an out put Voltage of the output stage and a reference Voltage, there is provided a minimum pulse width detector circuit that Sup plies a current to a phase compensation capacitor when the pulse width of the drive signal is at the minimum value, thus preventing the output Voltage from dropping below a value corresponding to the minimum value when the load fluctu ates, and improving transient response characteristics of the output Voltage. W D Ea W-PWM Wawm dry W2 CLR (b - 123 11 122 Delay W D2 (Tmin) ---------------------- - Delay W3 (Ts) D1 135 134 US 2012/0268093 A1 Oct. 25, 2012 Sheet 1 of 4 Patent Application Publication 09% AupA US 2012/0268093 A1 Oct. 25, 2012 Sheet 4 of 4 Patent Application Publication |- — US 2012/0268.093 A1 DC-DC CONVERTER CONTROL METHOD AND DC-DC CONVERTER CONTROL CIRCUIT CROSS-REFERENCE TO RELATED APPLICATION 0001. This application claims priority under 35 U.S.C. S119 from Japanese Patent Application No. 2011-097453, filed on Apr. 25, 2011, the entirety of which is incorporated herein by reference. BACKGROUND OF THE INVENTION 0002 1. Technical Field 0003. The present invention relates to a DC-DC converter control method and DC-DC converter control circuit. 0004 2. Related Art 0005. A switching type DC-DC converter with excellent conversion efficiency, like, for example, the reference tech nology of FIG.4, is widespread as a power conversion device that converts a direct current Voltage into another direct cur rent Voltage. 0006. The DC-DC converter of the reference technology shown in FIG. 4 includes a switching element SW and induc tor L connected in series to an output terminal that outputs an output Voltage Vout, a capacitor C connected between the output terminal and a ground potential (GND), a commutat ing diode D connected between a connection point of the Switching element SW and inductor L and the ground poten tial, a PWM signal generating circuit that generates a drive signal VdrV for controlling a turning on and off of the Switch ing element SW by pulse width modulation (PWM), voltage dividing resistors Rd1 and Rd2 that divide the output voltage Vout, generating a feedback Voltage Vd, an error amplifier, formed of a transconductance amplifier, that generates an output voltage Vea and inputs it into the PWM signal gener ating circuit, and a phase compensation capacitor CC con nected to an output of the error amplifier. 0007. The error amplifier, by injecting or discharging a current in accordance with the difference between the refer ence voltage Vref and the feedback voltage Vd, wherein the output voltage Vout is divided by the voltage dividing resis tors Rd1 and Rd2 and fed back, into or from the phase com pensation capacitor Ce, generates the output Voltage Vea, wherein the difference between the reference voltage Vref and feedback voltage Vd is amplified, as the voltage of the phase compensation capacitor Co. 0008. The PWM signal generating circuit generates a drive signal Vdrvin accordance with the output voltageVea of the error amplifier. In the PWM signal generating circuit, a minimum value Tmin is provided for a pulse width Todrv of the output drive signal VdrV, and when Vea drops beyond a control range, the drive signal VdrV having the minimum value Tmin for the pulse width Tarv is output. 0009 Herein, considering a case in which the load current decreases Suddenly due to a load mode change, or the like, the output voltage Vout rises, and the feedback voltage Vd also rises, owing to which the output voltage Vea of the error amplifier starts to drop. Even when the pulse width Tarv becomes as Small as the minimum value Tmin, the output voltage Vea of the error amplifier continues to drop provided that the feedback voltage Vd is higher than Vref (that is, provided that the output Voltage Vout exceeds a target value). Oct. 25, 2012 0010 Although not shown in FIG.4, it may be that, when operating the DC-DC converter under conditions wherein a rise of Vout is expected even when the pulse width of the drive signal VdrV becomes the minimum value Tmin, a circuit that detects an overvoltage and skips a pulse is provided, thus keeping the rise of Vout within a predetermined range. In this kind of case, the output voltage Vea of the error amplifier stabilizes in a condition in which it has dropped to a lower limit determined by the circuit configuration of the error amplifier. 0011. Herein, when the load current increases suddenly in a condition in which the output voltage Vea of the error amplifier has plummeted to the lower limit, Vea starts to rise again, but at this time, as time is needed until Vea reaches the PWM control range (the range in which the pulse width Todrv spreads beyond Tmin), there is a technical problem in that the drop of the output Voltage Vout increases. 0012. With regard to a minimum on time of the switching element, the technologies of JP-A-2008-187813 and JP-A- 2009-60439 are known. 0013. In JP-A-2008-187813, there is disclosed a technol ogy whereby, in a configuration in which the control of a switching element is switched between a PFM control and a PWM control depending on the size of a load, a minimum on period is set in the PWM control, an action turning off the Switching element is carried out when the current flowing through the Switching element exceeds an acceptable value after the minimum on period has elapsed, and the minimum on period is shorter than a PFM control on period. 0014. Meanwhile, in JP-A-2009-60439, there is disclosed a method whereby, recognizing the same kind of problem with regard to the recovery of the output voltage Vea of the error amplifier, the lower limit of the output voltage of the error amplifier is restricted by adapting the circuit configura tion of the error amplifier. 0015 With this kind of circuit, however, it is not possible to obtain an advantage unless the control range of the PWM signal generating circuit is coordinated with the lower limit of the output voltage of the error amplifier. When using a differ ential amplifier to configure a kind of circuit wherein current is Supplied to the phase compensation capacitor Ce when the output of the error amplifier drops below a predetermined voltage, it is possible to freely set the lower limit value, but when the PWM control range changes in accordance with operating conditions (for example, when Tminis a fixed value but the Switching frequency can be changed), it is difficult to respond using a method whereby Vea is given a fixed lower limit value in advance. SUMMARY OF THE INVENTION 0016. An object of the invention is to provide a technology whereby it is possible to realize an improvement in the tran sient response of an output Voltage to a load fluctuation, or the like, in a switching power source that carries out a PWM control. 0017. A first aspect of the invention provides a DC-DC converter control method including an error amplifier that amplifies and outputs the difference in voltage between a feedback Voltage output from an output stage and a reference Voltage, a phase compensation capacitor connected to an output of the error amplifier, and a PWM signal generating circuit wherein the pulse width of an output signal driving a Switching element of the output stage changes in accordance with the output voltage of the error amplifier, the method US 2012/0268.093 A1 including: setting a non-zero minimum value for the pulse width of the output signal of the PWM signal generating circuit; and Supplying a current to the phase compensation capacitor, based at least partly on the pulse width of the output signal acting at (e.g., having) the non-zero minimum value. 0018. A second aspect of the invention provides a DC-DC converter control circuit including an error amplifier that amplifies and outputs the difference in voltage between a feedback Voltage output from an output stage and a reference Voltage, a phase compensation capacitor connected to an output side of the error amplifier, and a PWM signal gener ating circuit that carries out a pulse width modulation (PWM) changing the pulse width of an output signal for a Switching element of the output stage in accordance with the output voltage of the error amplifier, wherein the PWM signal gen erating circuit includes a minimum pulse width setting circuit that sets a non-zero minimum value of the pulse width of the output signal for the Switching element, and a minimum pulse width detector circuit that supplies a current to the phase compensation capacitor based at least partly on the pulse width of the output signal acting at (e.g., having) the non-Zero minimum value. 0019. According to the invention, it is possible to provide a technology whereby it is possible to realize an improvement in the transient response of an output Voltage to a load fluc tuation, or the like, in a Switching power source that carries out a PWM control. BRIEF DESCRIPTION OF THE DRAWINGS 0020 FIG. 1 is a diagram showing one example of a con figuration of a DC-DC converter control circuit, which is one embodiment according to a control method and control cir cuit of the invention; 0021 FIG. 2 is a diagram showing in further detail one portion of the configuration of the DC-DC converter control circuit of FIG. 1, which is one embodiment according to the control method and control circuit of the invention; 0022 FIG. 3 is a timing chart showing one example of an action of the DC-DC converter control circuit, which is one embodiment according to the control method and control circuit of the invention; and 0023 FIG. 4 is a circuit diagram of a DC-DC converter of reference technology of the invention. DETAILED DESCRIPTION OF THE EMBODIMENTS 0024. In this embodiment, as one mode, a switching power source that carries out a PWM control is such that current is Supplied to a phase compensation capacitor when the pulse width of the PWM control is at a minimum value, thus pre venting a drop in the output Voltage of an error amplifier. 0025 Because of this, it is possible to prevent the output voltage of the error amplifier dropping beyond the lower limit of a PWM signal control range, thus achieving an improve ment in transient response. 0026. Hereafter, a detailed description will be given, while referring to the drawings, of the embodiment of the invention. 0027 FIG. 1 is a diagram showing one example of a con figuration of a DC-DC converter control circuit, which is one embodiment according to a control method and control cir cuit of the invention. 0028 FIG. 2 is a diagram showing in further detail one portion of the configuration of the DC-DC converter control Oct. 25, 2012 circuit of FIG. 1, which is one embodiment according to the control method and control circuit of the invention. 0029 FIG. 3 is a timing chart showing one example of an action of the DC-DC converter control circuit implementing the control method, which is one embodiment of the inven tion. 0030. A DC-DC converter M including a PWM signal generating circuit 110 of the embodiment shown in FIG. 1 differs from the reference technology of FIG. 4 in that a Tmin detector circuit is provided in the PWM signal generating circuit, and a current up is Supplied to a phase compensation capacitor CC when the pulse width is Tmin (that is, when the pulse width becomes smaller than Tmin in the event that a minimum pulse width Tmin is not provided). 0031. As shown in FIG. 1, the DC-DC converter M of the embodiment includes an output stage 200 comprising a switching element 210 (SW), direct current power source 250, inductor 220 (L), commutating diode 230 (D), and capacitor 240 (C), and a control circuit 100 for controlling a turning on and off of the switching element 210 of the output stage 200. 0032. In the case of the DC-DC converter M of the embodiment, the switching element 210 and inductor 220 of the output stage 200 are connected in series with a load, configuring a buck converter, reduce the direct current Volt age of the direct current power source 250, and output it to an output terminal 260. 0033. Also, the control circuit 100 includes the PWM signal generating circuit 110, an error amplifier 150 including a transconductance amplifier, and a phase compensation capacitor 160 (CC). 0034. The switching element 210 of the output stage 200, controlled on and off by a drive signal VdrV output from the PWM signal generating circuit 110, by opening and closing a connection path between the direct current power source 250 and the inductor 220, commutating diode 230, and capacitor 240, outputs a direct current output Voltage Vout in accor dance with the ratio between the path being open and closed to the output terminal 260. 0035 Also, the output voltage Vout becomes a feedback voltage Vd of the error amplifier 150 via a voltage dividing resistor 140. 0036. The error amplifier 150 amplifies the difference between a predetermined reference voltage Vrefand the feed back voltage Vd, which is the output voltage Vout of the output stage 200 divided and fed back by the voltage dividing resistor 140, and outputs an output voltage Vea to PWM signal generating circuit 110. More specifically, by injecting or discharging a current in accordance with the difference between the reference voltage Vref and feedback voltage Vd into or from the phase compensation capacitor Ce, the output voltage Vea, wherein the difference between the reference voltage Vref and feedback voltage Vd is amplified, is gener ated as the Voltage of the phase compensation capacitor Ce. 0037. Then, in the case of the embodiment, the PWM signal generating circuit 110 of the control circuit 100 includes a minimum pulse width detector circuit 130, to be described hereafter, wherein the minimum pulse width detec tor circuit 130 can supply the current Iup to the phase com pensation capacitor CC of the error amplifier 150 at a kind of timing to be described hereafter. 0038 Next, referring to FIG. 2, one example of an internal configuration of the PWM signal generating circuit 110 con