Old Exam 1 with Resolution - Advanced VLSI Design and Applications | ECEN 6263, Exams of Electrical and Electronics Engineering

Download Old Exam 1 with Resolution - Advanced VLSI Design and Applications | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263 Fall 2006 Exam | WRITE YOUR NAME HERE Ans Wey All questions must be answered on test paper! Open Book, Open Notes 1. Sketch a transistor level circuit diagram for a single bit scan register using the clocking strategies given below. Assume that the four clock lines, )), by, bo, by, are available, but not all of them need ta be used. The register outputs should change only on the ris- ing edge of , . Clearly label the D input, Q output, scanin, scanout and any clock inputs that you use. i qe a.True single phase clocking a Fi a 2 ? Stan out . f 4 _ of fin 7 Dp tt 8 ch Las b.Pseudo single phase clocking Sn é & , wot tl -CHL Slanin se sun J p rt Ch © 4 > pact ECEN 6263 Fall 2006 Exam 1’ October 6, 2006 Vy os c.True two phase clocking e ee Sat Ae _f ‘ — J ww d.Pseudo two phase clocking _ | 3 om _— ECEN 6263 Fall 2006 Exam i ‘October 6, 2006