Download Old Exam 1 with Solutions - Advanced VLSI Design and Applications | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263 .—
Fall 2000
Exam: 1.
WRITE YOUR NAME HERE Anew a
All questions must be answered on test paper!
Open Book, Open Notes
2 1. Find the transistor widths Wyeet, Wneetts Wapass for a 3 bus pair static RAM subject to
we the following constraints.
¢ For each transistor 42.< W< 402.
* Assume that the ratio of the bit line capacitance parameters is C,,/C,’ = 101.
* The read access delay should be as small as possible.
To. werk crveth, (ms 3)
Wath Mpa
Typos” ) Ta pos <|
For min, ved Arts}
Wrpors = [Go Wau = | or Maud
Gl” Wh %
el al shld be as by aa postrole (
hs ry Wn all =4on
Fen wn wg = [VID
This: sdlshow sthishies Maal
Miya so
Avy Wpectl S iD stitus “ed ¢ |
Ke ss -
>3¢
ECEN 6263:Fall2000-Exam b Ostober 4, 20060
2. Estimate the delays and power consumption in the circuit below using the RC model
developed.in class including the effects of the transistor threshold voltages V7, and
Vp. Use as parameters the channel resistances of the six transistors, Rj, ..., Rg, and the
node capacitances, Cj, ..., C4. You may assume that the capacitances already contain
all parasitics from the transistors and interconnect.
a. Answer the following when B = D =.1 and A goes from 0 to 1.
Initial voltage across C, 2 MaVee
Final voltage acrossC,?__ OF
Initial voltage across C2?) Volt
Final voltage across:C>?__./
Initial voltage across C3?__
Final voltage across C3? Va = Ver
Initial voltage across Cy? OO
Final voltage across Cy?__ Vad
Delay from A to X?
Vai tans = RC Ve-Vs) +R AR, )& Vie
V.
Stan = AG a +t RARe\ &
Delay from A to Y?
Vistiags RG luce) (KTR, \GMds t © GMa) ARG ad
diay 2 BG “yrs AR AR). +2,R; ade ut at Roy G
Average power dissipation assuming that-this situation occurs with probability p
C every T seconds?
P= Pele WurnS <QMu'+ & (pve) +e Vase
[o
Y)
ws
ECEN 6263 Fall 2000 Exam 1 ‘October 4, 2000 2