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Exam 3
April 18, 2002
Dr. W. Alan Doolittle
Print your name clearly and largely: So / urs Ga s
Instructions:
Read all the problems carefully and thoroughly before you begin working. You are allowed to
use 1 new sheet of notes (1 page front and back), your note sheets from the previous exams as
well as a calculator. There are 100 total points in this exam. Observe the point value of each
problem and allocate your time accordingly. SHOW ALL WORK AND CIRCLE YOUR
FINAL ANSWER WITH THE PROPER UNITS INDICATED. Write legibly. If I cannot read
it, it will be considered a wrong answer. Do all work on the paper provided. Turn in all scratch
paper, even if it did not lead to an answer. Report any and all ethics violations to the instructor.
Good luck!
Sign your name on ONE of the two following cases:
IDID NOT observe any ethical violations during this exam:
Tobserved an ethical violation during this exam:
c First 25% Multiple Choice, True/False (Select the most correct answer)
L). -(3-points) The gate current in the MOSFET is
a.) Highest under large positive gate bias
b.) Highest under large negative gate bias
¢.) Is determined by the change in fermi level position at the semiconductor-oxide interface
@: always zero
¢.) Is zero except in inversion
2.) (3-points) A depletion mode PMOS transistor has @..:
a.) ...p-type substrate.
© .i-type substrate
¢.) n-type channel when biased into cutoff (either depletion or accumulation)
d.) huge gate current.
3.) (4-points each, 12-points total) For the three transistor cross-sections I, I and I shown below,
answer each of the three questions a-c:
IIL,
a.) For Vos>Vps>0 which cross-sectional view (I, I or IID) is correct. 1
b.) For 0<Vgs<Vogs-Vt<Vps which cross-sectional view (I, II or II) is correct. =
©.) For Vgs<0 and Vps>0 which cross-sectional view , I or Il) is correct. . Tir
4.) (4-points) Which energy band diagram corresponds to a PMOS capacitor biased into accumulation.
a) b) ©.)
Wy \
d)
f)
=~
5.) (3-points) For a Transresistance amplifier designed for maximum gain (circle all that apply):
a.) You should have a high input impedance?
(6.))You should have a low input impedance?
¢.) You should have a high output impedance?
(4.) You should have a low output impedance?
CS The output is a voltage
Extra work can be done here, but clearly indicate with problem you are solving.
R,
in,
Vous
wv,
m3
Using Supe tyres 4 ton t
Ie Les wing v Ve hage
Step Ko tne
_ ites = Vin = ral fe Re
von inten! ~th vetting
: Stage
Step as ley Ain, = Vinge d 6
u
Extra work can be done here, but clearly indicate with problem you are solving.
Fane = inl PM vw BON ~ an, 9
re
| ane = Gin, + tM ing al
Ribs
Wn
; Vout
Vv
Method 4° d
Since the virtual graunol assures Varo, Ring = Rs or
Method 2. Vous + Ling Re # Rs) > Vin5
Sb Vous — Re Wing
R
=P - Vig (re = Vins
5
Re
Tiny (1 + zs ding (Re +R)
Ring > ry a (e185)
A ing
[Rs 8)
Pulling all the concepts together for a useful purpose: (4" portion}
8.) (45-points) Given the following circuit, what is the AC voltage gain, Vou/Vinac? You may
assume all capacitors have infinite capacitance and are thus, AC shorts. Additionally consider
the circuit to be operated at low frequencies where you can neglect ali small signal capacitances,
Grading will be based as such: 20 points for DC solution (Vas, Vos along with Ips for both
transistors), 5 points for the conversion to the small signal model and 20 points for the small
signal analysis.
Hint: Assume and then verify that both transistors are saturated, If M2 is saturated, identify
it’s functionality (i.e. what is M2 being used for) in the DC circuit.
Do not panic! Performing this identification will make the AC solution easier but is not
necessary to get the correct answer.
. Mt a WWe100u
he Lely
VinAC HY —>
1 Vout
1
tmeg | tk RL
M2 wWetodu} 1+
by Letu =
DoT
Use the following parameters:
For NMOS Depletion Transistors:
WV AP Ky=20 WAV? Vi=1.0V 4=0.0V' Length(L)=tum Width (W)=100 um
[a4 For NMOS Enhancement Transistors:
77 K,"=20 w/v? Vr1.0V 4=0.0 V7 Length (L)=1 um Width (W)=100 um
For PMOS Depletion Transistors:
Ky’=40 uA/V?—V4=43.0V A=0.1V" Length (L)=10um — Width (W)=10 um
For PMOS Enhancement Transistors:
K,’=40uA/V?—V7=-3.0V A=0.1.V' Length (L)=10um Width (W)=10 um