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Analogue Systems Design I Exam Questions and Instructions for EE211 Module, Exams of Materials science

The exam questions and instructions for the analogue systems design i module (ee211) in the fields of electrical & electronic engineering, electronic & computer engineering, energy systems engineering, engineering innovation - electronic, and sports and exercise engineering. The exam covers topics such as diode characteristics, semiconductor make-up of transistors, amplifier circuits, and filter design. Candidates are required to answer question 1, which is compulsory and carries 40 marks, and any three other questions, each carrying 20 marks. The exam duration is 3 hours, and the format includes multiple-choice questions, sketching, and calculations.

Typology: Exams

2012/2013

Uploaded on 03/25/2013

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Download Analogue Systems Design I Exam Questions and Instructions for EE211 Module and more Exams Materials science in PDF only on Docsity! EE211 Analogue Systems Design I Page 1 of 6 Autumn Examinations 2011-2012 Exam Code(s) 2BLE, 2BP, 2BSE, 2BEI, 2BEE Exam(s) Second Year Electrical and Electronic Engineering Second Year Electronic and Computer Engineering Second Year Energy Systems Engineering Second Year Engineering Innovation - Electronic Second Year Sports and Exercise Engineering Module Code(s) EE211 Module(s) Analogue Systems Design I Paper No. 1 External Examiner(s) Prof. G.W. Irwin Internal Examiner(s) Prof. G. Ó Laighin Dr. M. Duffy Dr. J.G. Breslin Instructions: Answer Question 1 and Any Three Other Questions Question 1 is compulsory and carries 40 marks Question 2, 3, 4 and 5 carry 20 marks each Candidates should note that marks may be lost if answers are not presented in a neat and legible format. Include rough-work calculations. Provide adequate information in your answers to illustrate your understanding. State any assumptions made in your answers. Duration 3 hours No. of Pages 6 pages (including cover page) Discipline(s) Electrical & Electronic Engineering Requirements: EE211 Analogue Systems Design I Page 2 of 6 Question 1 (a) Assuming ideal diode characteristics for D1 in Fig. 1.1, sketch the output voltage waveform, vo(t), for an input voltage, vi(t) = 5 sin(2000πt). Mark values of voltage and time on your sketch. [5 marks] Fig. 1.1 (b) Using a diagram, describe the semiconductor make-up of an npn Bipolar Junction Transistor (BJT). [5 marks] (c) Draw the Box Model of an amplifier circuit and explain why it is used in electronic circuit analysis. [5 marks] (d) Describe with the aid of a diagram the phenomenon known as pinch-off in an N- channel Junction Field Effect Transistor (JFET). [5 marks] (e) Draw the block diagram for a unity negative feedback system and the circuit diagram for an operational amplifier-based inverting amplifier. [5 marks] (f) For a differentiator circuit (differentiation amplifier) based on an operational amplifier, draw the circuit diagram and give an expression for the output voltage. [5 marks] (g) Calculate the values of resistor(s) and capacitor(s) required to provide a first-order active low-pass filter with a cut-off frequency of 1 kHz and a pass band gain of 3 (i.e. AF = 3). [5 marks] (h) Define what is meant by sensitivity, linearity and range as they relate to sensors. [5 marks] R L D 1 – + ~ vi(t) vo(t) + – EE211 Analogue Systems Design I Page 5 of 6 Question 4 (a) (i) Describe the semiconductor make-up of an N-channel E-MOSFET. [2 marks] (ii) Clearly explain the enhancement mode of operation for this N-channel E- MOSFET. [3 marks] (b) Draw the transfer characteristics for both an N-channel and a P-channel E-MOSFET, and for both an N-channel and a P-channel D-MOSFET. [5 marks] (c) For the MOSFET biasing circuit shown in Fig. 4.1, VDD = +18 V, R1 = 80 MΩ, R2 = 10 MΩ, RD = 3.2 kΩ and RS = 2 kΩ. The drain current IDSS = 10 mA for VGS = 0 V. Find the pinch-off voltage for the MOSFET and the quiescent output voltage. [10 marks] Fig. 4.1 EE211 Analogue Systems Design I Page 6 of 6 Question 5 (a) Describe how you would build a basic 3-bit DAC using an inverting summing amplifier, and detail the scenario whereby maximum current would be drawn from the digital circuit. [6 marks] (b) Draw the circuit for a zero level detector based on an operational amplifier comparator, and sketch the input and output voltages where a sinusoid VP sin ωt is being compared with a ground reference voltage. [4 marks] (c) For a Schmitt trigger with R1 = 65k, R2 = 10k, +VCC = + 15 V, -VCC = -15 V, Vin = 4 sin ωt, find both of the trigger points for the circuit, and then explain how the Schmitt trigger switches its output voltage by referencing what happens at various voltage levels along the input sine wave cycle (assume the output is initially at its maximum positive value). [10 marks]
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