VHDL Packages and Libraries: Sharing and Reusing VHDL Code with Packages and TextIO, Study notes of Electrical and Electronics Engineering

Download VHDL Packages and Libraries: Sharing and Reusing VHDL Code with Packages and TextIO and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 VHDL in Action Packages and Libraries Ch 3, pp. 96-114 Martin 2003 2 Last time Version of waveform updating algorithm to handle reject clauses Macro and micro time Delta delays: Ensure correct ordering of zero time events Martin 2003 3 Covered in This Lesson Packages Libraries TextIO Martin 2003 4 Motivation Why have subprograms? • Readability • Design re-use • Sharing Packages and libraries are the mechanism for design re-use and sharing Martin 2003 5 Packages Observations: • Including function and procedure declarations within ARCHITECTURE / PROCESS blocks is awkward. • Can't share between architectures • Not very readable • Not very maintainable • Have to cut/paste subprogram into every unit that uses it… Martin 2003 6 Packages (cont'd) Better approach: • Group logically related sets of functions and procedures into a module that can be easily shared among distinct designs and people. • Promote reuse • Easier to maintain • Package 2 Martin 2003 7 Package Preview A Package contains two parts: Package declaration: PACKAGE pname IS < prototypes of package components> END pname; Contains list of available package components, functions, types, procedures, etc. Martin 2003 8 Package Preview (cont'd) Package Body PACKAGE BODY pname IS < Contains package component definitions> END pname; A listing of the implementations of package components Martin 2003 9 Example Package(1 of 2) PACKAGE sub_std_logic_1164 IS TYPE std_ulogic IS ( 'U', --uninitialized 'X', -- forcing unknown '0', -- forcing 0 '1', -- forcing 1 'Z', -- high impedance 'W', -- weak unknown 'L', -- weak low 'H', -- weak high '-' -- don't care ); Martin 2003 10 Example Package(2 of 2) TYPE std_ulogic_vector IS ARRAY (Natural RANGE <>) OF std_ulogic; FUNCTION "AND" ( l, r : std_ulogic) RETURN std_ulogic; FUNCTION "AND" ( l, r : std_ulogic_vector) RETURN std_ulogic_vector; FUNCTION "AND" ( l : std_ulogic_vector, r : std_ulogic) RETURN std_ulogic_vector; COMPONENT dff PORT ( d, clk : IN std_ulogic; q : OUT std_ulogic); END COMPONENT; END sub_std_logic_1164; Martin 2003 11 Example Package Body PACKAGE BODY sub_std_logic_1164 IS FUNCTION "AND" ( l, r : std_ulogic) RETURN std_ulogic IS VARIABLE tmp : std_ulogic; BEGIN tmp := ‘1’ WHEN l = ‘1’ AND r=‘1’ ELSE ‘0’ WHEN l=‘0’ OR r=‘0’ ELSE ‘X’; RETURN( tmp); END “AND”; o o Martin 2003 12 Example Package Body FUNCTION "AND" ( l, r : std_ulogic_vector) RETURN std_ulogic_vector IS VARIABLE tmp : std_ulogic_vector; BEGIN ASSERT l’range = r’range; REPORT “Ranges must be equal for vector AND”; SEVERITY ERROR; FOR k in l’range LOOP tmp(k) := l(k) AND r(k); END LOOP; RETURN tmp; END “AND”; 5 Martin 2003 25 Libraries Successfully analyzed models are stored in a library A library may consist of several models which • may reference one another • may be arranged in a hierarchical fashion Two types of libraries: • WORK: current analysis entered here • RESOURCE: read-only reference libraries Martin 2003 26 Libraries Libraries contain PRIMARY and SECONDARY units: Primary units: • Entities • Package • Configuration Secondary units: • Architectures • Package bodies Primary units must be analyzed before corresponding secondary units. Both must be in the same library. Martin 2003 27 Library Names Libraries have LOGICAL and PHYSICAL names: Logical name: • Used by the VHDL model • Portable, independent of the simulator Physical name: • Used by the host operating system • Dependent upon host platform Martin 2003 28 Library Names The VHDL simulator must offer some means of mapping Logical names to Physical names: • In LDV, mapping is in the CDS.lib file: include $CDS_INST_DIR/tools/inca/files/cds.lib define work C:/tom/courses/4514f03/other_code/work • Indirectly, the global CDS.lib file has: DEFINE std ./STD DEFINE synopsys ./SYNOPSYS DEFINE ieee ./IEEE DEFINE ambit ./AMBIT Martin 2003 29 Making Libraries Visible To make a library visible, entry must exist in mapping file In your VHDL code, visibility controlled by LIBRARY command: LIBRARY WORK; -- Automatic in all VHDL models LIBRARY IEEE; Access to library components is done with the USE command: USE IEEE.Std_Logic_1164.ALL; -- In the library IEEE, make the package -- STD_LOGIC_1164 visible to the -- following entity. Martin 2003 30 Creating Libraries Implementation dependent In LDV: • Edit->Add->New Library • Give a logical name and a directory • File->Set work library • Set this to the logical name • Analyze code into the library • Add library/use clauses to your other models • Be sure to set work library back to your original work library 6 Martin 2003 31 Where the libraries roam In default install of LDV, IEEE packages are in • C:\Program Files\Cadence Design Systems\LDV\tools\inca\files\IEEE.src • std_logic_1164 package: std_logic_1164.vhd • It’s useful to look through the packages for functions you can use…We’ll go through them in class next week. Martin 2003 32 TextIO Files can be distinguished by the type of information stored Package TEXTIO • Declares: type line is access string; type text is file of string ; • Use STD.TextIO.all; VHDL 1987: • file infile : text is in “inputdata. txt”; • file outfile : text is out “outputdata. txt”; Martin 2003 33 Using TextIO: Example procedure read_v1d(variable f:in text; v:out std_logic_vector) is variable buf : line; variable c : character ; begin -- do not forget appropriate library declarations readline (f , buf ); --read a line from the file. for i in v ’range loop read( buf , c ) ; --read a character from the line. case c is when ‘X’ => v (i) := ‘X’ ; when ‘U’ => v (i) := ‘U’ ; when ‘Z’ => v (i) := ‘Z’ ; when ‘0’ => v (i) := ‘0’ ; when ‘1’ => v (i) := ‘1’ ; when ‘-’ => v (i) := ‘-’ ; when ‘W’ => v (i) := ‘W’ ; when ‘L’ => v (i) := ‘L’ ; when ‘H’ => v (i) := ‘H’ ; when others => v (i) := ‘0 ’; end case; end loop; end; (From Yalamanchili) Martin 2003 34 TextIO and testbenches Remember: Testbench instantiates the system to be tested and a stimulus driver Stimulus can be from: • “on the fly” generation • local constant arrays • file I/O Can also save results to file for later viewing… Martin 2003 35 Summary Packages and libraries • Share your VHDL code with friends and neighbors… TextIO Next time: Review for midterm