VHDL Packages: Declarations, Bodies, Use Clauses and Standard Packages, Slides of Computer Science

Download VHDL Packages: Declarations, Bodies, Use Clauses and Standard Packages and more Slides Computer Science in PDF only on Docsity! Packages and Use Clauses Docsity.com Outline • Package Declarations • Package bodies • Use Clauses • Standard Packages Docsity.com Package Declarations • EBNF: see page 232 • Example (Figure 8.1): package cpu_types is constant word_size : positive := 16; constant address_size : positive := 24; subtype word is bit_vector(word_size - 1 downto 0); subtype address is bit_vector(address_size - 1 downto 0); type status_value is ( halted, idle, fetch, mem_read, mem_write, io_read, io_write, int_ack ); end package cpu_types; Docsity.com Package Declarations • Package declarative item – Type – Subtype – Constant – Signal – Subprograms – Alias – … Docsity.com Package Declarations • A package is another form of design unit • A package is analyzed and placed into the working directory as a library unit • Selected name of an item in a package – Library_Name.Package_Name.item – Ex. Work.cpu_type.status_value – Ex. Fig 8.2 • Packages can be shared among models – Ex. Fig 8.3, 8.4 and 8.5 Docsity.com architecture fsm of bus_sequencer is -- NOTE: it uses the clock signals from clock_pkg to synchronize the fsm. signal next_state_vector : -- . . .; begin bus_sequencer_state_register : entity work.state_register(std_cell) port map ( phi1 => work.clock_pkg.clock_phase1, phi2 => work.clock_pkg.clock_phase2, next_state => next_state_vector, -- . . . ); end architecture fsm; Fig 8.5 Docsity.com Package Declarations • Note different VHDL suites provide different ways of specifying the library into which a library unit is placed. • Global signals can be declared in packages. – A global signal can affect overall behavior of a system (not by port but by global signal) – Global signals should be used sparingly. – Ex Fig 8.3 Docsity.com Subprograms, constants in Package Declaration • Constants, Procedures and functions can be declared in a package • Example: subtype word32 is bit_vector(31 downto 0); procedure add ( a, b : in word32; result : out word32; overflow : out boolean ); function "<" ( a, b : in word32 ) return boolean; constant max_buffer_size : positive; Docsity.com Package Body • Package declarations provide external views (interfaces) and package bodies provide the implementation (information hiding) • If a package declaration only includes types, signals, constants, then there is no need to have package body • EBNF: see page 239 • The package_body_declarative_item must include the full declarations (implementation) of all subprograms defined in the corresponding package declaration. Docsity.com package bit_vector_signed_arithmetic is function "+" ( bv1, bv2 : bit_vector ) return bit_vector; function "-" ( bv : bit_vector ) return bit_vector; function "*" ( bv1, bv2 : bit_vector ) return bit_vector; -- . . . end package bit_vector_signed_arithmetic; Fig 8.8 Docsity.com package body bit_vector_signed_arithmetic is function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . . function "-" ( bv : bit_vector ) return bit_vector is -- . . . function mult_unsigned ( bv1, bv2 : bit_vector ) return bit_vector is return bit_vector( "*"(unsigned(bv1), unsigned(bv2)) ); end function mult_unsigned; function "*" ( bv1, bv2 : bit_vector ) return bit_vector is begin if bv1(bv1'left) = '0' and bv2(bv2'left) = '0' then return mult_unsigned(bv1, bv2); elsif bv1(bv1'left) = '0' and bv2(bv2'left) = '1' then return -mult_unsigned(bv1, -bv2); elsif bv1(bv1'left) = '1' and bv2(bv2'left) = '0' then return -mult_unsigned(-bv1, bv2); else return mult_unsigned(-bv1, -bv2); end if; end function "*"; end package body bit_vector_signed_arithmetic; Fig 8.8 Docsity.com Use Clauses • Another Example: use work.cpu_types.word, work.cpu_types.address; variable data_word : word; variable next_address : address; • Importing all of the names defined in a package: library.package.ALL – Example: use ieee.std_logic_1164.all; Docsity.com architecture behavioral of cpu is begin interpreter : process is use work.cpu_types.all; variable instr_reg : word; variable instr_opcode : opcode; begin -- . . . -- initialize loop -- . . . -- fetch instruction instr_opcode := extract_opcode ( instr_reg ); case instr_opcode is when op_nop => null; when op_breq => -- . . . -- . . . end case; end loop; end process interpreter; end architecture behavioral; Fig 8.9 Docsity.com Predefined Package Standard • Standard package defines some contents that will be used for all designs (Appendix B) – TYPE: boolean, bit, character, sensitive_level, integer, time, bit_vector – SUBTYPE: natural, positive, delay_length – Function: now, (>,<,… for integer, bit_vector, ..) • VHDL includes an implicit context clause library std, work, use std.standard.all at the beginning of each design unit. Docsity.com IEEE std_logic_1164 • IEEE standard package std_logic_1164 defines types and operations for models that need to deal with strong, weak and high-impedance strength and with unknown values – Multi-value logic systems • Check types and functions in your CAD tools Docsity.com Standard VHDL Synthesis Package • IEEE standard packages numeric_bit and numeric_std define arithmetic operations on integers represented using vectors of bit and std_logic element respectively • Most synthesis tools accept models using these types and operations for numeric computations • IEEE standard for synthesizable models specifies that these are the only types that can be used Docsity.com Standard VHDL Synthesis Package • Appendix A describes the topics of synthesis of VHDL model in more detail. • Appendix C lists numeric_bit and numeric_std packages • See Fig 8.11 on page 247 Docsity.com