OS Lecture 10: Paging Mechanisms - Optimizations & Advanced Features - Prof. Geoffrey M. V, Study notes of Computer Science

Download OS Lecture 10: Paging Mechanisms - Optimizations & Advanced Features - Prof. Geoffrey M. V and more Study notes Computer Science in PDF only on Docsity! CSE 120 Principles of Operating Systems Spring 2009 Lecture 10: Paging Geoffrey M. Voelker May 12, 2009 CSE 120 – Lecture 10 – Paging 2 Lecture Overview Today we’ll cover more paging mechanisms:  Optimizations  Managing page tables (space)  Efficient translations (TLBs) (time)  Demand paged virtual memory (space)  Recap address translation  Advanced Functionality  Sharing memory  Copy on Write  Mapped files May 12, 2009 CSE 120 – Lecture 10 – Paging 5 Two-Level Page Tables Page table Master page number Secondary Virtual Address Master Page Table Page frame Offset Physical Address Physical Memory Offset Page frame Secondary Page Table May 12, 2009 CSE 120 – Lecture 10 – Paging 6 Addressing Page Tables Where do we store page tables (which address space)?  Physical memory  Easy to address, no translation required  But, allocated page tables consume memory for lifetime of VAS  Virtual memory (OS virtual address space)  Cold (unused) page table pages can be paged out to disk  But, addressing page tables requires translation  How do we stop recursion?  Do not page the outer page table (called wiring)  If we’re going to page the page tables, might as well page the entire OS address space, too  Need to wire special code and data (fault, interrupt handlers) May 12, 2009 CSE 120 – Lecture 10 – Paging 7 Efficient Translations  Our original page table scheme already doubled the cost of doing memory lookups  One lookup into the page table, another to fetch the data  Now two-level page tables triple the cost!  Two lookups into the page tables, a third to fetch the data  And this assumes the page table is in memory  How can we use paging but also have lookups cost about the same as fetching from memory?  Cache translations in hardware  Translation Lookaside Buffer (TLB)  TLB managed by Memory Management Unit (MMU) May 12, 2009 CSE 120 – Lecture 10 – Paging 10 Managing TLBs (2)  OS ensures that TLB and page tables are consistent  When it changes the protection bits of a PTE, it needs to invalidate the PTE if it is in the TLB  Reload TLB on a process context switch  Invalidate all entries  Why? What is one way to fix it?  When the TLB misses and a new PTE has to be loaded, a cached PTE must be evicted  Choosing PTE to evict is called the TLB replacement policy  Implemented in hardware, often simple (e.g., Last-Not-Used) May 12, 2009 CSE 120 – Lecture 10 – Paging 11 Paged Virtual Memory  We’ve mentioned before that pages can be moved between memory and disk  This process is called demand paging  OS uses main memory as a page cache of all the data allocated by processes in the system  Initially, pages are allocated from memory  When memory fills up, allocating a page in memory requires some other page to be evicted from memory » Why physical memory pages are called “frames”  Evicted pages go to disk (where? the swap file/backing store)  The movement of pages between memory and disk is done by the OS, and is transparent to the application May 12, 2009 CSE 120 – Lecture 10 – Paging 12 Page Faults  What happens when a process accesses a page that has been evicted? 1. When it evicts a page, the OS sets the PTE as invalid and stores the location of the page in the swap file in the PTE 2. When a process accesses the page, the invalid PTE will cause a trap (page fault) 3. The trap will run the OS page fault handler 4. Handler uses the invalid PTE to locate page in swap file 5. Reads page into a physical frame, updates PTE to point to it 6. Restarts process  But where does it put it? Have to evict something else  OS usually keeps a pool of free pages around so that allocations do not always cause evictions May 12, 2009 CSE 120 – Lecture 10 – Paging 15 TLB Misses  At this point, two other things can happen 1. TLB does not have a PTE mapping this virtual address 2. PTE exists, but memory access violates PTE protection bits  We’ll consider each in turn May 12, 2009 CSE 120 – Lecture 10 – Paging 16 Reloading the TLB  If the TLB does not have mapping, two possibilities: 1. MMU loads PTE from page table in memory » Hardware managed TLB, OS not involved in this step » OS has already set up the page tables so that the hardware can access it directly 2. Trap to the OS » Software managed TLB, OS intervenes at this point » OS does lookup in page table, loads PTE into TLB » OS returns from exception, TLB continues  A machine will only support one method or the other  At this point, there is a PTE for the address in the TLB May 12, 2009 CSE 120 – Lecture 10 – Paging 17 TLB Misses (2) Note that:  Page table lookup (by HW or OS) can cause a recursive fault if page table is paged out  Assuming page tables are in OS virtual address space  Not a problem if tables are in physical memory  Yes, this is a complicated situation  When TLB has PTE, it restarts translation  Common case is that the PTE refers to a valid page in memory » These faults are handled quickly, just read PTE from the page table in memory and load into TLB  Uncommon case is that TLB faults again on PTE because of PTE protection bits (e.g., page is invalid) » Becomes a page fault… May 12, 2009 CSE 120 – Lecture 10 – Paging 20 Sharing  Private virtual address spaces protect applications from each other  Usually exactly what we want  But this makes it difficult to share data (have to copy)  Parents and children in a forking Web server or proxy will want to share an in-memory cache without copying  We can use shared memory to allow processes to share data using direct memory references  Both processes see updates to the shared memory segment » Process B can immediately read an update by process A  How are we going to coordinate access to shared data? May 12, 2009 CSE 120 – Lecture 10 – Paging 21 Sharing (2)  How can we implement sharing using page tables?  Have PTEs in both tables map to the same physical frame  Each PTE can have different protection values  Must update both PTEs when page becomes invalid  Can map shared memory at same or different virtual addresses in each process’ address space  Different: Flexible (no address space conflicts), but pointers inside the shared memory segment are invalid (Why?)  Same: Less flexible, but shared pointers are valid (Why?)  What happens if a pointer inside the shared segment references an address outside the segment? May 12, 2009 CSE 120 – Lecture 10 – Paging 22 Copy on Write  OSes spend a lot of time copying data  System call arguments between user/kernel space  Entire address spaces to implement fork()  Use Copy on Write (CoW) to defer large copies as long as possible, hoping to avoid them altogether  Instead of copying pages, create shared mappings of parent pages in child virtual address space  Shared pages are protected as read-only in parent and child » Reads happen as usual » Writes generate a protection fault, trap to OS, copy page, change page mapping in client page table, restart write instruction  How does this help fork()? May 12, 2009 CSE 120 – Lecture 10 – Paging 25 Summary Paging mechanisms:  Optimizations  Managing page tables (space)  Efficient translations (TLBs) (time)  Demand paged virtual memory (space)  Recap address translation  Advanced Functionality  Sharing memory  Copy on Write  Mapped files Next time: Paging policies May 12, 2009 CSE 120 – Lecture 10 – Paging 26 Next time…  Still Chapter 9