Docsity
Docsity

Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity


Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan


Guidelines and tips
Guidelines and tips

Parallel Processing Architectures - Intro to Computer Architecture - Lecture Slides, Slides of Computer Architecture and Organization

During the course work of the Intro to Computer Architecture, we study the main concept regarding the:Parallel Processing Architectures, Parallel Computers, Type of Interconnection, Bit Level Parallelism, Instruction Level Parallelism, Amdahl’s Law, Flynn’s Classification, Classification of Computer Systems, Shared Address

Typology: Slides

2012/2013

Uploaded on 05/06/2013

anurati
anurati 🇮🇳

4.1

(23)

128 documents

1 / 18

Toggle sidebar

Related documents


Partial preview of the text

Download Parallel Processing Architectures - Intro to Computer Architecture - Lecture Slides and more Slides Computer Architecture and Organization in PDF only on Docsity! Parallel Processing Architectures Docsity.com Parallel Computers • Definition: “A parallel computer is a collection of processing elements that cooperate and communicate to solve large problems fast.” • Questions about parallel computers: – How large a collection? – How powerful are processing elements? – How do they cooperate and communicate? – How are data transmitted? – What type of interconnection? – What are HW and SW primitives for programmer? – Does it translate into performance? Docsity.com Why Multiprocessors? 1. Microprocessors as the fastest CPUs • Collecting several much easier than redesigning 1 2. Complexity of current microprocessors • Do we have enough ideas to sustain 2X/1.5yr? • Can we deliver such complexity on schedule? • Limit to ILP due to data dependency 3. Slow (but steady) improvement in parallel software (scientific apps, databases, OS) 4. Emergence of embedded and server markets driving microprocessors in addition to desktops • Embedded functional parallelism • Network processors exploiting packet-level parallelism • SMP Servers and cluster of workstations for multiple users – Less demand for parallel computing Docsity.com PARALLEL COMPUTING Amdahl’s Law: The speed-up of a program is given by 1 1 Sn= @4(1-% yn - OC when n= Where, n = number of processors and @ = sequential fraction of the program « If & =0, the maximum speed-up is n. However, the actual speed-up will be much less due to fixed memory size, interprocessor communication and synchronization delays. ® Docsity.com Amdahl’s Law and Parallel Computers • A portion is sequential => limits parallel speedup – Speedup <= 1/ (1-FracX) • Ex. What fraction sequetial to get 80X speedup from 100 processors? Assume either 1 processor or 100 fully used 80 = 1 / [(FracX/100 + (1-FracX)] 0.8*FracX + 80*(1-FracX) = 80 - 79.2*FracX = 1 FracX = (80-1)/79.2 = 0.9975 • Only 0.25% sequential! Docsity.com Classification of Parallel Processors • SIMD – EX: Illiac IV and Maspar • MIMD - True Multiprocessors 1. Message Passing Multiprocessor: Interprocessor communication through explicit “send” and “receive” operation of messages over the network EX: IBM SP2, NCUBE, and Clusters 2. Shared Memory Multiprocessor: Interprocessor communication by load and store operations to shared memory locations. EX: SMP Servers, SGI Origin, HP V-Class, Cray T3E Docsity.com Shared Address/Memory Model • Communicate via Load and Store – Oldest and most popular model • Based on timesharing: processes on multiple processors vs. sharing single processor • Single virtual and physical address space – Multiple processes can overlap (share), but ALL threads share a process address space • Writes to shared address space by one thread are visible to reads of other threads – Usual model: share code, private stack, some shared heap, some private heap Docsity.com Shared Address Model Summary • Each process can name all data it shares with other processes • Data transfer via load and store • Data size: byte, word, ... or cache blocks • Uses virtual memory to map virtual to local or remote physical • Memory hierarchy model applies: now communication moves data to local proc. cache (as load moves data from memory to cache) – Latency, BW (cache block?), scalability when communicate? Docsity.com Communication Models • Shared Memory – Processors communicate with shared address space – Easy on small-scale machines – Advantages: • Model of choice for uniprocessors, small-scale MPs • Ease of programming • Lower latency • Easier to use hardware controlled caching • Message passing – Processors have private memories, communicate via messages – Advantages: • Less hardware, easier to design • Focuses attention on costly non-local operations • Can support either SW model on either HW base Docsity.com Advantages shared-memory communication model • Compatibility with SMP hardware • Ease of programming when communication patterns are complex or vary dynamically during execution • Ability to develop apps using familiar SMP model, attention only on performance critical accesses • Lower communication overhead, better use of BW for small items, due to implicit communication and memory mapping to implement protection in hardware, rather than through I/O system • HW-controlled caching to reduce remote comm. by caching of all data, both shared and private. Docsity.com Advantages message-passing communication model • The hardware can be simpler • Communication explicit => simpler to understand; in shared memory it can be hard to know when communicating and when not, and how costly it is • Explicit communication focuses attention on costly aspect of parallel computation, sometimes leading to improved structure in multiprocessor program • Synchronization is naturally associated with sending messages, reducing the possibility for errors introduced by incorrect synchronization • Easier to use sender-initiated communication, which may have some advantages in performance Docsity.com
Docsity logo



Copyright © 2024 Ladybird Srl - Via Leonardo da Vinci 16, 10126, Torino, Italy - VAT 10816460017 - All rights reserved