Download Parameters - Microelectronic Devices and Circuits - Exam and more Exams Microelectronic Circuits in PDF only on Docsity! University of California at Berkeley College of Engineering Dept. of Electrical Engineering and Computer Sciences EE 105 Midterm 1 Spring 2006 Prof. Ming C. Wu Problem Points Score 1 20 2 40 3 10 4 10 5 20 Total 100 • You may use a calculator • Show all your work and reasoning on the exam in order to receive full or partial credit. • Write your answer in the designated page for each problem. If you need more space, use the “Additional Space” at the end. • Please put a box around the final answer of each sub-problem • Time: 90 minutes Please use the following parameters for all problems unless specified otherwise: Φn+ = 550 mV, Φp+ = -550mV, Vth = 26mV εSi = 11.7, εSiO2 = 3.9, ε0 = 8.854 x 10 -14 F/cm, Q = 1.6 x 10-19 C, ni = 10 10 cm -3 1. Consider a silicon PN junction diode with an N-doping concentration of 10 16 cm -3 and a P-doping concentration of 10 18 cm -3 . Their cross-sectional area of the diode is 100 um 2 . Assume the reverse saturation current of the diode is 10 -14 Amp. The diode is forward biased at 0.7V. a) [10pt] Find the dynamic resistance at this bias. b) [10pt] Find the depletion capacitance at this bias. 2. Consider a MOS capacitor with a P+ polysilicon gate and an N-doped substrate with a doping concentration of 10 16 cm -3 . The thickness of the oxide is 230nm. a) [10pt] Find the threshold voltage. b) [10pt] Which mode is the MOS capacitor in when its gate is biased at 1V? c) [10pt] What is the maximum capacitance per unit area? d) [10pt] What is the minimum capacitance pr unit area? 3. [10pt] For the MOS capacitor in Problem (2), plot the charge density distribution as a function of position when the gate is biased at –2V. Please be as quantitative as possible. Show the positions of all charges, and show the magnitude and polarity of the charges. 4. [10pt] If the P+ gate of the MOS capacitor in Problem (2) is replaced by a metal whose electrostatic potential is 0V. What is the threshold boltage of the new MOS capacitor? 5. Consider an N-MOSFET with an N+ polysilicon gate on P-type substrate (Na = 10 17 cm -3 ). The source is grounded, and the drain is biased at 5V. The transistor has a gate length of 1 um, and a width of 10 um. The thickness of the gate oxide is 10 nm. For simplicity, assume the channel-length modulation parameter λ = 0. a) [10pt] At what gate voltage does the transistor turn on, i.e., start to have significant current flowing between source and drain? b) [10pt] Find the drain current when the gate is biased at 2V.
