Download Parasitic Capacitance Models in CSCE 613 - Lectures 23 & 24 by Dr. James P. Davis and more Study notes Computer Science in PDF only on Docsity! 2002/4/29 Department of Computer Science & Engineering Spring 2002 © 2002 Dr. James P. Davis CSCE 613 – Lectures 23 & 24 Parasitic Capacitance Models Page 2Dr. James P. Davis Lecture 23 - Outline Resistance Models Resistance calculations for conducting layers Sheet resistance Rs for metal. Sheet resistance for Polysilicon. Resistance for Diffusion. Resistance calculations for non-rectangular areas Resistance calculations Rc for Transistor-forming channel areas. Resistance calculations for Contacts and Vias. Capacitance Models MOS Capacitor calculation ‘Co’ (without Source and Drain). Load Capacitance Gate capacitance (of inputs connected to output of gate). Diffusion Capacitance (drain regions connected to outputs). Routing Capacitance (of connections between outputs and other inputs). Page 5Dr. James P. Davis MOS Capacitance Definition: We consider the capacitance effects of the Gate to substrate (Bulk), without accounting for the Source or Drain. This will establish a baseline Co from which we add results from other capacitance calculations as we evolve the model. Behavior: The capacitance-voltage characteristic depends on the “state” of the substrate surface: Accumulation: the MOS structure acts like a parallel plate capacitor. Depletion: additional capacitance is created as a result of voltage creating a depleted region under surface of substrate. Inversion: the presence of higher voltage creates region of high conductivity in the channel. Page 6Dr. James P. Davis Gate Capacitance-1 Definition: We define a set of individual “lumped” capacitances associated with the Gate region and the substrate. Now we consider the effect of capacitance associated with Source and Drain regions as well. Behavior: Total Gate capacitance is the sum of individual ones as shown in the circuit diagram. Gate-to-channel: has 3 regions of operation. Off region Non-saturated region Saturation Charge-based model: use approximation. Unit transistor: assume general sizing for ease of calculation during layout. Page 7Dr. James P. Davis Gate Capacitance-2 Off region: Non-saturated region: Saturated region: Page 10Dr. James P. Davis Routing Capacitance-1 VLSI Engineer (f rom Use Case View) Calculate Routing Capacitance SingleWireCapacitance MultipleConductorCapacitance Since there are multiple routing layers, the capacitance between layers can become complex. LineToGroundCapacitance LineToLineCapacitance CrossoverCapac itance <<PartOf>> <<PartOf>> <<PartOf>> Page 11Dr. James P. Davis Routing Capacitance-2 Definition – Single Wire Routing capacitance between metal and poly layers and the substrate can be approximated using parallel plate model. Effect of “fringing fields” is to increase the area of the capacitor plates. Capacitance between adjacent conductors also affect this calculation. Approximations Fringing Fields: sub-divide the regions into the rectangular and the cylindrical (for the “fringed” end caps) with width: w – t/2, cylindrical radius: t/2. Modeling with these effects yield higher values for capacitance than predicted with parallel plate model. cf: equations 4.14, 4.15 (pg. 192). Page 12Dr. James P. Davis Routing Capacitance-3 Definition – Multi-Wire Modern CMOS processes have multiple routing layers, and interactions can be complex. Simulations (3-D) are too complex, therefore we seek approximations that are reasonably accurate. Routing structure model: (1) top ground plane, (2) conductor being modeled, (3) bottom ground plane. Approximations Line to ground capacitance: Line to line capacitance: Crossover capacitance: The equations for A, B weighting factors, and their components, are given in 4.18a,b, pg. 194.
