Design and Analysis of Parasitic RLC in FETs - Prof. Louis Johnson, Study notes of Electrical and Electronics Engineering

Download Design and Analysis of Parasitic RLC in FETs - Prof. Louis Johnson and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! E C E N 4 3 0 3 D i g i t a l V L S I D e s i g n Parasitic R,L and C Resistance p. 198 eq. 4.33, 4.34 sheet resistance def. Fig. 4.32 p.198 calculating resistance I I (same as 4 squares in series) R Rs 4 1 --⋅= R 4 Rs 1 1 --⋅×= I I (same as 4 squares in paral- lel) R Rs 1 4 --⋅= R 14 -- Rs 1 1 --⋅×= Note: L defined parallel to current and W defined perpendicular to current. L W When cur- rent flow lines are parallel, . R LW ----∼ Current flow lines not always parallel! Corners I I results same as if square on the corner only counts . R 2.5Rs= 1 2 --Rs Table 4.7 p. 200 sheet resistance values (0.18µm process)Parasitic R,L and C August 25, 2009 page 1 of 19 E C E N 4 3 0 3 D i g i t a l V L S I D e s i g n Fig. 4.31 p. 197 Metal layers have different sheet resistances because of different thick- nesses. Example calculation: The shape below is fabricated in a layer with Rs 15Ω= . 12λ 8λ 4λ 12λ 4λ 1 sq 1 sq 1 sq 1 sq 1 sq1/2 sq R 5.5Rs= 82.5Ω= Channel “Resistance” max “on” resistance |VGS| = VDD |ID| ohmic resistance VDD |VDS| From the figure, it is clear that the average channel resistance, Ron, is Rohmic Ron Rmaxon< < For small VDS, FET will be “ohmic” ID β VGS VT–( )VDS AbulkVDS 2 2⁄–[ ] 1 VDS EsatL( )⁄+ --------------------------------------------------------------------------------= 1 Rohmic ---------------VDS= Rohmic 1 β VGS VT– --------------------------- whereβ κWL ----=,=∴ Rohmic 1 κ VGS VT– ---------------------------- L W ----= Parasitic R,L and C August 25, 2009 page 2 of 19 E C E N 4 3 0 3 D i g i t a l V L S I D e s i g n large contact contact mask 4λ 2λ Each contact is made from minimum size contacts. Large contacts are really made of parallel combinations of minimum size contacts. conducting layer => metal1 metal1 conducting layer The resistance of multiple contacts can be determined from the parallel combination of minimum contacts. Rcontact Rmin n ----------= Rmin resistance of min size contact. ( )= n no. of min contacts ( ) contact area ( )min contact area ( ) --------------------------------------------- contact area ( ) 6λ 6λ⋅ ----------------------------------= = = The resistance of the contact structure should be added to the resistance of the conducting layers since they are in series. Rc n -----Rs m1( ) Lm1 Wm1 ---------- Lm1 Rs ndiff( ) Lndiff Wndiff ------------- Lndiff Wm1 Wndiff RTOT Rm1 Rcont Rndiff+ += For example Note: When calculating resistance for classwork, we will measure lengths, L, from the center of a contact as shown above. Parasitic R,L and C August 25, 2009 page 5 of 19 E C E N 4 3 0 3 D i g i t a l V L S I D e s i g n Capacitance +Q -Qd area A Q CV= C εAd -----= V + - L W tox C εoxWL tox ---------------= C εox tox ------    WL= C CA ---    WL= process constant Same area => same capacitance (independent of shape!) Fig. 2.2 p. 68 MOS capacitor (isolated) a. accumulation C Cox εox tox ------ A=≅ b. depletion C 1– Cdep εsi d ----- A=    1– Cox( ) 1–+≅ Cox Cdep gate substrate channel c. inversion C Cox≅ All conducting layers over silicon substrate have this dependence, not just the gate of a FET. Can show depletion layer thickness d Vdep Nsub ----------∼ Vdep: voltage across depletion Nsub: doping of substrate High doping => small d => large Cdep => higher VT for inversion. Thus everywhere except where we want transistors we put “channel stop” high doping of substrate to pre- vent inversion where we do not want transistors.Parasitic R,L and C August 25, 2009 page 6 of 19 E C E N 4 3 0 3 D i g i t a l V L S I D e s i g n n+ channel stop n-well conducting layer Cp+ p+ This prevents channel formation under conducting layers at normal bias voltages. C no channel stop with channel stop V Vdd Cox (no inversion for bias below Vdd) Therefore, can approximate C Cox≈ for all layers except poly over thin oxide where transistors form and except for diffusions which are down inside the silicon instead of above the oxide. MOS Device Capacitance Fig. 2.14 p. 83 Note: Csb, Cdb are diff. cap! Table 2.1 p. 78 Note: Cgd drops off at high Vds (saturation region) because most channel charge is nearer to source in saturation G S D Q Gate Capacitance The total gate capacitance is Cg Cgs Cgb Cgd+ += Cox A --------    WL≤ where Cox A --------    εox tox ------= Detailed circuit simulators, like SPICE, can take into account the non-linearities of the gate capacitance (see Fig. 2.11, p. 79). For hand calculations, the simpler oxide capaci- tance is used to approximate the gate capacitance,Parasitic R,L and C August 25, 2009 page 7 of 19 E C E N 4 3 0 3 D i g i t a l V L S I D e s i g n It is more important to include overlap capacitance in modern deep submicron processes. Example gate capacitance calculation for 0.18µm process. λ 0.09µm= L 2λ= 0.18µm= W 4λ= 0.36µm= XL 0= XW 0.01µm–=, LINTn 0.016µm= WINTn 0.0µm= Leffn 0.148µm= Weffn 0.35µm= LINTp 0.028µm= WINTp 0.0µm= Leffp 0.124µm= Weffp 0.35µm= Cg Cox A -------- W L⋅ ⋅= 8.5fF µm2⁄ 0.36µm 0.18µm⋅ ⋅= 0.55fF= Cgn Cox A --------    Weffn Leffn⋅ ⋅ Cgson P ------------    Weffn⋅ Cgdon P -------------    Weffn⋅ Cgbon P -------------    2⋅ Leffn+ + += 8.5fF µm2⁄( ) 0.35µm 0.148µm⋅ ⋅ 0.79fF µm⁄( ) 2 0.35µm⋅ ⋅ 0+ += 0.44fF 0.56fF+= 1.00fF= Cgp Cox A --------    Weffp Leffp⋅ ⋅ Cgsop P ------------    Weffp⋅ Cgdop P -------------    Weffp⋅ Cgbop P -------------    2⋅ Leffp+ + += 8.5fF µm2⁄( ) 0.35µm 0.124µm⋅ ⋅ 0.64fF µm⁄( ) 2 0.35µm⋅ ⋅ 0+ += 0.37fF 0.45fF+= 0.82fF= Diffusion Layer Capacitance n+ n+P Cd Cd: junction capacitance of reverse biased p-n diode Cd Cj 1 V φ ---+    m–= φ 0.8 to 0.9V≅ m 13 -- to 12 --≅Parasitic R,L and C August 25, 2009 page 10 of 19 E C E N 4 3 0 3 D i g i t a l V L S I D e s i g n Vdd Cd Cd V 0 Detailed circuit simulators, like SPICE, can model this. For hand calculations we approx. Cd V( ) Cd≈ as average cap over operating voltage range 0 to Vdd. Cd 1 Vdd ------- Cd V( ) Vd 0 Vdd ∫= 1 Vdd ------- Cj 1 V φ --+    m– Vd 0 Vdd ∫= Cjφ 1 mj–( )VDD ------------------------------ 1 VDD φ ---------+    1 mj– 1–= Fig. 2.13 p. 81 diff cap from layout There are two different types of sidewall capacitance n+ p+ p- Trench Oxide reduces sidewall cap sidewall capacitance next to trench oxide sidewall capacitance next to gate side view top view L D W Channel Stop The total capacitance from the n-diffusion on the right is thenParasitic R,L and C August 25, 2009 page 11 of 19 E C E N 4 3 0 3 D i g i t a l V L S I D e s i g n Cdiff Cnd A --------    WD Cnd P --------    2D W+( ) Cndg P ----------    W+ += where Cnd A --------    n-diff cap per unit area = Cnd P --------    n-diff cap per unit perimeter next to thick oxide = Cndg P ----------    n-diff cap per unit perimeter next to gate = Here the dimensions are clear. In the corresponding equation 2.16 on p.80, the dimensions are not clear. Capacitance for poly-over-thick-oxide and metal layers First consider an interconnection wire that is isolated from other wires, but not from the substrate as in left side of Fig. 4.34, p. 201 Fig. 4.35, p. 201 gives Eq. 4.36. Note that C = (...)WL + (...)L Another approximation is in Eq. 4.37 = (plate cap) + (fringe cap) All layers have plate capacitance term linearly dependent on W and a fringe capacitance term independent of W. W L C A ---    cap/unit-area (plate cap) C P ---    cap/unit-perimeter (fringe cap) CTOT C A ---    W L CP ---    2W 2L+( )+⋅ ⋅= This is a good model for capacitive coupling to the substrate when no other layers are nearby. Cross Coupling Capacitance Now consider an interconnection wire that has another conducting wire nearby as in the right side of fig. 4.34, p. 201. Capacitance calculations are more complex with multiple metal layers. Fig. 4.36, p. 202 Modern processes have metal (and poly) layers with high thickness to width ratios. This makes fringing capacitance much more important than in older processes. The fringing fields are very complex and there is no general closed form solution.Parasitic R,L and C August 25, 2009 page 12 of 19 E C E N 4 3 0 3 D i g i t a l V L S I D e s i g n Layer Ci/A Ci/P Ci/L poly m1 89 50 124 m2 71 39 98 m3 68 39 96 m4 68 44 106 m5 64 44 105 m6 34 32 94 Ci/L is the total capacitance per unit length in layer i. Ci L⁄ Ci A⁄( )Wi 2 Ci P⁄( )+= The authors report Ci/L as approximately 0.2 fF/µm whereas the calculations above are closer to 0.1 fF/µm. The discrepancy is probably due to the authors assuming a metal plane in the layers above and below while we have included spaces between wires in lay- ers above and below. Also, the widths and spacings used by the authors were smaller than the scalable design rules used above. A good number to use is somewhere between 0.1 and 0.2 fF/µm for metal wires in modern processes. Capacitance of contacts and vias C1 substrate contact overlap area C2 side view top view Overlap area of contact should be included when computing cap of bottom layer, but should not be included in cap of top layer.Parasitic R,L and C August 25, 2009 page 15 of 19 E C E N 4 3 0 3 D i g i t a l V L S I D e s i g n C1: C2: 4 10 4 4 8 A = 10x2 + 4x4 + 4x4 = 52λ2 (overlap area of contact counts) P = 4+4+4+2+10+4+4+4+2+10 = 48λ (boundary between poly conductor and contact overlap does not count) A = 4x8 = 32 λ2 (area of contact does not count) P = 8 + 4 + 8 = 20 λ (boundary between poly conductor and contact overlap does not count) 4 The same arguments can be made for all other layers where the capacitive coupling to the substrate dominates (diffusion layers). For metal interconnect in modern processes where cross-coupling capacitance dominates, the situation is slightly different. side view CTOT Ci Cj Cij–+= All of the capacitance from both lines is still present except the Cij which is shorted out by the contact or via.Parasitic R,L and C August 25, 2009 page 16 of 19 E C E N 4 3 0 3 D i g i t a l V L S I D e s i g n Inductance L I V + - V = L dI dt ---- Note: In this section, L means inductance, and l means length. Typically, wires inside a chip have inductance proportional to the wire length, 0.15pH µm⁄ Ll -- 1.5pH µm⁄< < but this can be misleading because the true inductance depends on the complicated geom- etry of the entire current loop including the power and ground lines. Taking into account the parasitic resistance, capacitance and inductance, a wire should be modeled as an RLC transmission line (fig. 4.46b, p. 214). However, when comparing the waveforms in fig. 4.46c, leaving the inductance out does not change the results signifi- cantly, and the wire can be modeled as an RC transmission line (fig. 4.46a) in most practi- cal cases. The inductance cannot be left out when the wire inductive impedance is greater in magni- tude than the wire resistive impedance. Leaving out the resistance gives us a lossless transmission line where electromagnetic signals propagate at the speed of light within the material. One can show that this speed is v 1 L l --    C l ---    ---------------------- 1 εoxµ0 ----------------- c εox ε0⁄ --------------------= = = where we have used the magnetic permeability of free space (4π x 10-7H/m = 1.25pH/µm) because the materials used for wires are non-magnetic. c is the speed of light in vacuum (3 x 108 m/sec = 300 µm/psec). Unless the wire is superconducting, the resistance will cause significant losses if the wire is long enough. In the next section, we show that the propagation delay for an RC transmission line is td RC( ) 1 2 -- R l ---    C l ---    l2= If we compare with the lossless case where td LC( ) l v - l Ll --    C l ---   = = we find that the resistance dominates for long lines and the inductance dominates for short lines. The boundary between the two regions corresponds equal LC and RC delays at l 2R l⁄( ) ------------- L l⁄( ) C l⁄( ) -------------=Parasitic R,L and C August 25, 2009 page 17 of 19